PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 90

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
7.7
Data EEPROM memory has its own code-protect bits in
configuration words. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 22.0
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
TABLE 7-1:
DS39616B-page 88
INTCON
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
LOOP
Name
Operation During Code-Protect
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
BRA
BCF
BSF
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register2 (not a physical register)
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
GIE/GIEH
EEPGD
OSFIP
OSFIF
OSFIE
Bit 7
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
Loop
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
PEIE/GIEL TMR0IE
CFGS
Bit 6
—
—
—
Bit 5
—
—
—
—
FREE
INTE
EEIP
EEIE
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
Bit 4
EEIF
Preliminary
WRERR
RBIE
Bit 3
—
—
—
7.8
The Data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124 or D124A.
If this is not the case, an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
Note:
Bit 2
Using the Data EEPROM
If data EEPROM is only used to store con-
stants and/or data that changes rarely, an
array refresh is likely not required. See
specification D124 or D124A.
Bit 1
INTF
WR
—
—
—
CCP2IP 1--1 -1-1 1--1 -1-1
CCP2IF 0--0 -0-0 0--0 -0-0
CCP2IE 0--0 -0-0 0--0 -0-0
Bit 0
RBIF
RD
 2003 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xx-0 x000 uu-0 u000
POR, BOR
Value on:
—
Value on
all other
Resets
—