PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 259

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20.9
Figure 20-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins. The internal A/D RC oscillator must
be selected to perform a conversion in Sleep.
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT3:ACQT0
bits are set to ‘010’, and selecting a 4 T
time before the conversion starts.
FIGURE 20-3:
FIGURE 20-4:
 2003 Microchip Technology Inc.
GO bit is set,
and holding
cap is
disconnected
from analog
input
A/D triggered
Note 1:
1
A/D Conversions
Note 1:
T
Automatic
Acquisition
Time
ACQT
2
In continuous modes, next conversion starts at the end of T
Cycles
Conversion time is a minimum of 11 T
Conversion Starts
3
A/D CONVERSION T
A/D CONVERSION T
T
AD
b9
1 T
4
AD
b8
Conversion Starts
(Holding capacitor is disconnected)
2 T
T
AD
b9
1 T
AD
b7
AD
3 T
AD
b8
acquisition
2 T
AD
b6
PIC18F2331/2431/4331/4431
Go bit cleared on the rising edge of Q1 after the first Q3
following T
AD
AD
4 T
AD
b7
CYCLES (A
CYCLES (A
Preliminary
3 T
AD
b5
5 T
AD
b6
AD
Go bit cleared on the rising edge of Q1 after the first Q3
following T
4 T
AD
b4
AD
11
6 T
T
(1)
AD
+ 2 T
b5
AD
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The resulting buffer loca-
tion will contain the partially completed A/D conversion
sample. This will not set the ADIF flag, therefore, the
user must read the buffer location before a conversion
sequence overwrites it.
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
, and result buffer is loaded.
CQT
5 T
AD
CQT
b3
Cycles
Note:
AD
CY
7 T
AD
<2:0> = 000, T
AD
b4
, and a maximum of 11 T
<3:0> = 0010, T
11
wait is required before the next acquisition can
6 T
AD
b2
(1)
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
and result buffer is loaded.
AD
b3
T
7 T
AD
AD
b1
12.
9 T
AD
b2
AD
8
ACQ
b0
10
T
ACQ
AD
b1
T
AD
= 0)
9 T
11
AD
= 4 T
AD
b0
+ 6 T
10
DS39616B-page 257
AD
T
AD
CY
)
.
11