PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 204

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
17.8.2
PWM output may be manually overridden for each
PWM channel by using the appropriate bits in the
OVDCOND and OVDCONS registers. The user may
select the following signal output options for each PWM
output pin operating in the Independent mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
Refer to Section 17.10 “PWM Output Override” for
details for all the override functions.
FIGURE 17-19:
17.9
The single pulse PWM operation is available only in
Edge-aligned mode. In this mode, the PWM module will
produce single pulse output. Single-pulse operation is
configured when the PTMOD1:PTMOD0 bits are set to
‘01’ in PTCON0 register. This mode of operation is use-
ful for driving certain types of ECMs.
In Single-pulse mode, the PWM I/O pin(s) are driven to
the active state when the PTEN bit is set. When the
PWM timer match with Duty Cycle register occurs, the
PWM I/O pin is driven to the inactive state. When the
PWM timer match with the PTPER register occurs, the
PTMR register is cleared, all active PWM I/O pins are
driven to the inactive state, the PTEN bit is cleared, and
an interrupt is generated, if the corresponding interrupt
bit is set.
17.10 PWM Output Override
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states
independent of the duty cycle comparison units. The
PWM override bits are useful when controlling various
types of ECMs like a BLDC motor.
DS39616B-page 202
Note:
Single-Pulse PWM Operation
PWM CHANNEL OVERRIDE
PTPER and PDC values are held as it is
after the single pulse output. To have
another cycle of single pulse, only PTEN
has to be enabled.
+V
PWM1
CENTER-CONNECTED
LOAD
PWM0
LOAD
Preliminary
OVDCOND and OVDCONS registers are used to
define the PWM override options. The OVDCOND
register contains eight bits, POVD7:POVD0, that
determine which PWM I/O pins will be overridden. The
OVDCONS
POUT7:POUT0, that determine the state of the PWM
I/O pins when a particular output is overridden via the
POVD bits.
The POVD bits are active-low control bits. When the
POVD bits are set, the corresponding POUT bit will
have no effect on the PWM output. In other words, the
pins corresponding to POVD bits that are set will have
the duty PWM cycle set by the PDC registers. When
one of the POVD bits is cleared, the output on the cor-
responding PWM I/O pin will be determined by the
state of the POUT bit. When a POUT bit is set, the
PWM pin will be driven to its active state. When the
POUT bit is cleared, the PWM pin will be driven to its
inactive state.
17.10.1
The even-numbered PWM I/O pin has override restric-
tions when a pair of PWM I/O pins are operating in the
Complementary mode (PMODx = 0). In Complemen-
tary mode, if the even-numbered pin is driven active by
clearing the corresponding POVD bit and by setting
POUT bits in OVDCOND and OVDCONS registers, the
output signal is forced to be the complement of the
odd-numbered I/O pin in the pair (see Figure 17-2 for
details).
17.10.2
If the OSYNC bit in the PWMCON1 register is set, all
output overrides performed via the OVDCOND and
OVDCONS registers will be synchronized to the PWM
time base. Synchronous output overrides will occur on
following conditions:
• When the PWM is in Edge-aligned mode, syn-
• When the PWM is in Center-aligned mode,
chronization occurs when PTMR is zero.
synchronization occurs when PTMR is zero and
when the value of PTMR matches PTPER.
Note 1: In the Complementary mode, the even
2: Dead time inserted to the PWM channels
COMPLEMENTARY OUTPUT MODE
OVERRIDE SYNCHRONIZATION
channel cannot be forced active by a fault
or override event when the odd channel is
active. The even channel is always the
complement of the odd channel with dead
time inserted, before the odd channel can
be driven to its active state as shown in
Figure 17-20.
even when they are in Override mode.
register
 2003 Microchip Technology Inc.
contains
eight
bits,