PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 40
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2331/2431/4331/4431
3.4
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Wake-up from a power-managed run mode can be trig-
gered by an interrupt, or any Reset, to return to full
power operation. As the CPU is executing code in run
modes, several additional exits from run modes are
possible. They include exit to Sleep mode, exit to a cor-
responding idle mode, and exit by executing a RESET
instruction. While the device is in any of the power-
managed run modes, a WDT time-out will result in a
WDT Reset.
3.4.1
The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microcontroller operates in this mode (a SLEEP instruc-
tion is executed to enter all other power-managed
modes). All other power-managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
FIGURE 3-9:
DS39616B-page 38
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Run Modes
Q1
PRI_RUN MODE
SEC_RUN MODE
Q2
PC
Q3
Q4
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1
1
2
3
Clock Transition
4
Preliminary
5
PC + 2
6
7
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01, and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
When a wake event occurs, the peripherals and CPU
continue to be clocked from the Timer1 oscillator while
the primary clock is started. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set, and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The primary clock is started. When the pri-
mary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the pri-
mary clock provides the system clock. The IDLEN and
SCS bits are not affected by the wake-up.
Note:
8
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, a forced
NOP will be executed instead and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, system clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2
Q3
2003 Microchip Technology Inc.
Q4
Q1
PC + 2
Q2
Q3
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