PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 140

• Manufacturer Part Number: PIC18F4431-I/P
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4431-I/P

• A/d Inputs: 9-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
12.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
FIGURE 12-1:
FIGURE 12-2:
DS39616B-page 138
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1CKI/T1OSO
T1CKI/T1OSO
Timer1 Operation
T1OSI
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag Bit
T1OSI
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
High Byte
TMR1H
Timer 1
8
TMR1H
T1OSC
8
TMR1
TMR1
Oscillator
T1OSCEN
Enable
T1OSCEN
Enable
Oscillator
TMR1L
TMR1L
8
CLR
(1)
(1)
Preliminary
CLR
Internal
Clock
F
OSC
Clock
Internal
F
/4
TMR1ON
OSC
CCP Special Event Trigger
On/Off
TMR1CS
/4
TMR1ON
CCP Special Event Trigger
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/
T1CKI
TRISC1:TRISC0 value is ignored, and the pins are
read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
1
0
on/off
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1SYNC
pins
Prescaler
1, 2, 4, 8
T1CKPS1:T1CKPS0
T1SYNC
0
1
Prescaler
1, 2, 4, 8
2
become
1
0
2
 2003 Microchip Technology Inc.
Synchronized
Clock Input
Peripheral Clocks
inputs.
Synchronized
Synchronize
Clock Input
Peripheral Clocks
Synchronize
det
That
det
is,
the