PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 71
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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TABLE 5-2:
2003 Microchip Technology Inc.
PTPERL
PTPERH
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
PDC3L
PDC3H
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
FLTCONFIG
OVDCOND
OVDCONS
CAP1BUFH/
VELRH
CAP1BUFL/
VELRL
CAP2BUFH/
POSCNTH
CAP2BUFL/
POSCNTL
CAP3BUFH/
MAXCNTH
CAP3BUFL/
MAXCNTL
CAP1CON
CAP2CON
CAP3CON
DFLTCON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and serial programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only.
PWM Time Base Period register (Lower 8 bits).
PWM Duty Cycle #0L register (Lower 8 bits)
PWM Duty Cycle #1L register (Lower 8 bits)
PWM Duty Cycle #2L register (Lower 8 bits)
PWM Duty Cycle #3L register (Lower 8 bits)
PWM Special Event Compare register (Lower 8 bits)
Capture 1 register, High Byte/
Velocity register, High Byte
Capture 1 register Low Byte/
Velocity register, Low Byte
Capture 2 register, High Byte/
QEI Position Counter register, High Byte
Capture 2 Reg., Low Byte/
QEI Position Counter register, Low Byte
Capture 3 Reg., High Byte/
QEI Max. Count Limit register, High Byte
Capture 3 Reg., Low Byte/
QEI Max. Count Limit register, Low Byte
SEVOPS3
= unknown,
POVD7
POUT7
DTPS1
Bit 7
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
UNUSED
UNUSED
UNUSED
UNUSED
u
SEVOPS2
CAP1REN
CAP2REN
CAP3REN
PWMEN2
FLT4EN
= unchanged, – = unimplemented,
POVD6
DTPS0
POUT6
FLTBS
Bit 6
UNUSED
UNUSED
SEVOPS1
FLTBMOD
PWMEN1
FLT3EN
POVD5
POUT5
Bit 5
DT5
—
—
—
SEVOPS0
PIC18F2331/2431/4331/4431
PWMEN0
FLTBEN
FLT2EN
POVD4
POUT4
Bit 4
DT4
PWM Duty Cycle #0H register (Upper 6 bits)
PWM Duty Cycle #1H register (Upper 6 bits)
PWM Duty Cycle #2H register (Upper 6 bits)
PWM Duty Cycle #3H register (Upper 6 bits)
—
—
—
Preliminary
q
= value depends on condition
SEVTDIR
FLTCON
CAP1M3
CAP2M3
CAP3M3
PMOD3
FLT1EN
POVD3
POUT3
PWM Special Event Compare reg (Upper 4 bits)
PWM Time Base Period register (Upper 4 bits)
Bit 3
DT3
CAP1M2
CAP2M2
CAP3M2
FLTCK2
PMOD2
POVD2
POUT2
FLTAS
Bit 2
DT2
—
FLTAMOD
CAP1M1
CAP2M1
CAP3M1
PMOD1
FLTCK1
POVD1
POUT1
UDIS
Bit 1
DT1
CAP1M0
CAP2M0
CAP3M0
FLTAEN
FLTCK0
PMOD0
OSYNC
POVD0
POUT0
Bit 0
DT0
-0-0 0000
-0-0 0000
-0-0 0000
-000 0000
1111 1111
---- 1111
--00 0000
0000 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
---- 0000
-101 0000
0000 0-00
0000 0000
-000 0000
1111 1111
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
DS39616B-page 69
Details on
52, 187
52, 188
52, 200
52, 208
52, 203
52, 204
53, 163
53, 163
53, 163
53, 178
page:
184
184
184
184
184
184
184
184
184
184
N/A
N/A
52,
52
52
52
53
53
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