PIC18F4431-I/P Microchip Technology Inc., PIC18F4431-I/P Datasheet - Page 238
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PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4431-IP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
A/d Inputs
9-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2331/2431/4331/4431
19.3.5
The enhanced USART module has the capability of
sending the special break character sequences that
are required by the LIN bus standard. The break char-
acter transmit consists of a Start bit, followed by 12 ‘0’
bits and a Stop bit. The frame break character is sent
whenever the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set, while the transmit shift register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the break character (typically, the sync char-
acter in the LIN specification).
Note that the data value written to the TXREG for the
break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or idle, just as it does during normal transmis-
sion. See Figure 19-9 for the timing of the break
character sequence.
FIGURE 19-9:
DS39616B-page 236
Reg. Empty Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
TX (pin)
TXIF bit
SENDB
BREAK CHARACTER SEQUENCE
SEND BREAK CHARACTER SEQUENCE
Dummy Write
SENDB Sampled Here
Start Bit
Bit 0
Preliminary
Bit 1
Break
19.3.5.1
The following sequence will send a message frame
header made up of a break, followed by an auto-baud
sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
19.3.6
The enhanced USART module can receive a break
character in two ways.
The first method forces to configure the baud rate at a
frequency of 9/13 the typical speed. This allows for the
Stop bit transition to be at the correct sampling location
(13 bits for break versus Start bit and 8 data bits for typ-
ical data).
The second method uses the auto-wake-up feature
described in Section 19.3.4 “Auto-Wake-up on
SYNC BREAK Character”. By enabling this feature,
the USART will sample the next two transitions on RX/
DT, cause an RCIF interrupt, and receive the next data
byte followed by another interrupt.
Note that following a break character, the user will
typically want to enable the auto-baud rate detect
feature. For both methods, the user can set the ABD bit
before placing the USART in its Sleep mode.
Configure the USART for the desired mode.
Set the TXEN and SENDB bits to setup the
break character.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the break has been sent, the SENDB bit is
reset by hardware. The sync character now
transmits in the Pre-Configured mode.
RECEIVING A BREAK CHARACTER
Break and Sync Transmit Sequence
Bit 11
Auto-Cleared
2003 Microchip Technology Inc.
Stop Bit
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