LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 43
LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
IC ETHER SW 3PORT 16BIT 56QFN
Manufacturer
SMSC
Specifications of LAN9303-ABZJ
Controller Type
Ethernet Switch Controller
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
190mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Switches
Standard Supported
Yes
Data Rate
10 Mbps/100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
0.19 A (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1095 - EVALUATION BOARD FOR LAN9303
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1082
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
4.2.1
4.2.1.1
4.2.1.2
RESET SOURCE
Digital Reset
Virtual PHY
Port 2 PHY
Port 1 PHY
nRST Pin
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire device. Configuration
straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A chip-level reset
is initiated by assertion of any of the following input events:
Chip-level reset/configuration completion can be determined by first polling the
Register
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the
(READY)
Ready (READY)
With the exception of the
(BYTE_TEST), and
forbidden while the
Device Ready (READY)
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the device, or if the power is removed
and reapplied to the device. This event resets all circuitry within the device. Configuration straps are
latched, and the EEPROM Loader is run as a result of this reset.
A POR reset typically takes approximately 23mS, plus an additional 91uS per byte of data loaded from
the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in approximately
6.0 seconds.
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the
device. Use of this reset input is optional, but when used, it must be driven for the period of time
specified in
are latched, and the EEPROM Loader is run as a result of this reset.
Power-On Reset (POR)
nRST Pin Reset
POR
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
bit of the
Section 14.5.2, "Reset and Configuration Strap Timing," on page
X
X
X
Table 4.1 Reset Sources and Affected Device Circuitry
bit indicates that the reset has completed and the device is ready to be accessed.
Hardware Configuration Register (HW_CFG)
Device Ready (READY)
Reset Control Register
X
X
X
bit is set.
Hardware Configuration Register
X
X
X
DATASHEET
X
X
X
X
X
43
(RESET_CTL), read access to any internal resources is
bit is cleared. Writes to any address are invalid until the
X
X
X
X
X
X
(HW_CFG),
X
X
X
until it is set. When set, the
X
X
X
Byte Order Test Register
351. Configuration straps
X
X
X
Revision 1.4 (07-07-10)
Byte Order Test
Device Ready
X
X
Device
X
X
X
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