LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 225

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.1.3
BITS
31:9
8:7
4:3
6
5
2
1
0
RESERVED
RESERVED
Note:
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of Switch Fabric interrupts due to the
Buffer Manager via the
(BM_IPR). The status bits in the
(SW_IPR)
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of Switch Fabric interrupts due to the
Switch Engine via the
The status bits in the
register are not affected.
RESERVED
Note:
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 2 MAC via the MAC_IPR_2 register (see
page
(SW_IPR)
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 1 MAC via the MAC_IPR_1 register (see
page
(SW_IPR)
Port 0 MAC Interrupt Mask (MAC_0)
When set, prevents the generation of Switch Fabric interrupts due to the
Port 0 MAC via the MAC_IPR_0 register (see
page
(SW_IPR)
Switch Global Interrupt Mask Register (SW_IMR)
This read/write register contains the global interrupt mask for the Switch Fabric interrupts. All switch
related interrupts in the
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked Switch Fabric interrupt is generated in the
Interrupt Pending Register
(SWITCH_INT)
on page 55
270). The status bits in the
270). The status bits in the
270). The status bits in the
These bits must be written as 11b
These bits must be written as 11b
register are not affected.
register are not affected.
register are not affected.
register are not affected.
Register #:
for more information.
bit in the
Switch Engine Interrupt Pending Register
Switch Global Interrupt Pending Register (SW_IPR)
Buffer Manager Interrupt Pending Register
Switch Global Interrupt Pending Register (SW_IPR)
Interrupt Status Register
0004h
DESCRIPTION
(SW_IPR), the interrupt will trigger the
Switch Global Interrupt Pending Register
Switch Global Interrupt Pending Register
Switch Global Interrupt Pending Register
Switch Global Interrupt Pending Register
DATASHEET
225
Section 13.4.2.44, on
Section 13.4.2.44, on
Section 13.4.2.44, on
Size:
(INT_STS). Refer to
(SWE_IPR).
32 bits
Switch Fabric Interrupt Event
Chapter 5, "System Interrupts,"
TYPE
may be masked via this
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.4 (07-07-10)
Switch Global
DEFAULT
11b
11b
1b
1b
1b
1b
1b
-