LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 146

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.2.2.3
31:22
21:16
BITS
15:6
5:0
RESERVED
GPIO Interrupt Enable[5:0] (GPIO[5:0]_INT_EN)
When set, these bits enable the corresponding GPIO interrupt.
Note:
RESERVED
GPIO Interrupt[5:0] (GPIO[5:0]_INT)
These signals reflect the interrupt status as generated by the GPIOs. These
interrupts are configured through the
Register
Note:
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
This read/write register contains the GPIO interrupt status bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into the
(INT_STS). Writing a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a
source. Status bits will still reflect the status of the interrupt source regardless of whether the source
is enabled as an interrupt in this register. The
Interrupt Enable Register (INT_EN)
occur. Refer to
The GPIO interrupts must also be enabled via the
Event Enable (GPIO_EN)
(INT_EN), in order to cause the interrupt pin (IRQ) to be asserted.
(GPIO_CFG).
As GPIO interrupts, GPIO inputs are level sensitive and must be
active greater than 40 nS to be recognized as interrupt inputs.
Offset:
Chapter 5, "System Interrupts," on page 55
1E8h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
bit of the
General Purpose I/O Configuration
DATASHEET
GPIO Interrupt Event (GPIO)
must also be set in order for an actual system level interrupt to
146
Interrupt Enable Register
Size:
GPIO Interrupt Event Enable (GPIO_EN)
GPIO Interrupt
for additional information.
32 bits
bit of the
TYPE
R/WC
Interrupt Status Register
R/W
SMSC LAN9303/LAN9303i
RO
RO
DEFAULT
Datasheet
bit of the
0h
0h
-
-