LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 207

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.3.2.10
BITS
9:5
3:0
15
14
13
12
11
10
4
Auto-MDIX Control (AMDIXCTRL)
This bit is responsible for determining the source of Auto-MDIX control for
Port x. When set, the Manual MDIX and Auto MDIX straps
(manual_mdix_strap_1/auto_mdix_strap_1
manual_mdix_strap_2/auto_mdix_strap_2
and Auto-MDIX functions are controlled using the AMDIXEN and
AMDIXSTATE bits of this register. When cleared, Auto-MDIX functionality is
controlled by the Manual MDIX and Auto MDIX straps by default. Refer to
Section 4.2.4, "Configuration Straps," on page 45
definitions.
0: Port x Auto-MDIX determined by strap inputs (
1: Port x Auto-MDIX determined by bits AMDIXEN and AMDIXSTATE
bits
Note:
Auto-MDIX Enable (AMDIXEN)
When the AMDIXCTRL bit of this register is set, this bit is used in
conjunction with the AMDIXSTATE bit to control the Port x Auto-MDIX
functionality as shown in
Auto-MDIX State (AMDIXSTATE)
When the AMDIXCTRL bit of this register is set, this bit is used in
conjunction with the AMDIXEN bit to control the Port x Auto-MDIX
functionality as shown in
RESERVED
SQE Test Disable (SQEOFF)
This bit controls the disabling of the SQE test (Heartbeat). SQE test is
enabled by default.
0: SQE test enabled
1: SQE test disabled
Receive PLL Lock Control (VCOOFF_LP)
This bit controls the locking of the receive PLL. Setting this bit to 1 forces
the receive PLL 10M to lock on the reference clock at all times. When in this
mode, 10M data packets cannot be received.
0: Receive PLL 10M can lock on reference or line as needed (normal
operation)
1: Receive PLL 10M locked onto reference clock at all times
RESERVED
10Base-T Polarity State (XPOL)
This bit shows the polarity state of the 10Base-T.
0: Normal Polarity
1: Reversed Polarity
RESERVED
Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
This read/write register is used to control various options of the Port x PHY.
The values of
indicated in the
Strap State Port 2
(HW_CFG).
Index (decimal): 27
auto_mdix_strap_1
AMDIX_EN Strap State Port 1
Table
Table
bits of the
DESCRIPTION
13.12.
13.12.
DATASHEET
Hardware Configuration Register
for Port 2 PHY) are overridden,
for Port 1 PHY,
and
207
auto_mdix_strap_2
for configuration strap
Size:
Table 13.13
and the
AMDIX_EN
)
16 bits
are
Note 13.66
Note 13.66
Note 13.66
Note 13.66
Note 13.66
NASR
NASR
NASR
NASR
NASR
TYPE
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Revision 1.4 (07-07-10)
DEFAULT
0b
0b
0b
0b
0b
0b
-
-
-