LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 162

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
13.2.4.7
BITS
31:0
EEPROM Address
Physical Address[31:0]
This field contains the lower 32-bits (31:0) of the physical address of the
Switch Fabric MACs.
Table 13.3 SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering
01h
02h
03h
04h
05h
06h
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)
This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This
r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h
(SWITCH_MAC_ADDRH). The contents of this register are optionally loaded from the EEPROM at
power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte
(bits [31:24]) is loaded from address 04h of the EEPROM. The Host can update the contents of this
field after the initialization process has completed.
Refer to
Table 13.3
registers with respect to the reception of the Ethernet physical address. Also shown is the correlation
between the EEPROM addresses and the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH
registers.
F o r e x a m p l e , i f t h e d e s i r e d E t h e r n e t p h y s i c a l a d d r e s s i s 1 2 - 3 4 - 5 6 - 7 8 - 9 A - B C , t h e
SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH registers would be programmed as shown in
Figure
shown.
13.2. The values required to automatically load this configuration from the EEPROM are also
Offset:
Section 8.4, "EEPROM Loader," on page 113
illustrates the byte ordering of the SWITCH_MAC_ADDRL and SWITCH_MAC_ADDRH
SWITCH_MAC_ADDRL[23:16]
SWITCH_MAC_ADDRL[31:24]
SWITCH_MAC_ADDRH[15:8]
SWITCH_MAC_ADDRL[15:8]
SWITCH_MAC_ADDRH[7:0]
SWITCH_MAC_ADDRL[7:0]
Register Location Written
1F4h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
162
S w i t c h F a b r i c M A C A d d r e s s H i g h R e g i s t e r
Size:
for information on using the EEPROM Loader.
32 bits
Order of Reception on Ethernet
TYPE
R/W
SMSC LAN9303/LAN9303i
2
3
5
1
4
6
nd
rd
th
th
th
st
FF0F8000h
DEFAULT
Datasheet