LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 179

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

No Flow Control Enabled
Symmetric Pause
Asymmetric Pause
Towards Switch
Asymmetric Pause
Towards MAC
Symmetric Pause
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
BITS
4:0
7
6
5
100BASE-X Half Duplex
This bit indicates the emulated link partner PHY 100BASE-X half duplex
capability.
0: 100BASE-X half duplex ability not supported
1: 100BASE-X half duplex ability supported
10BASE-T Full Duplex
This bit indicates the emulated link partner PHY 10BASE-T full duplex
capability.
0: 10BASE-T full duplex ability not supported
1: 10BASE-T full duplex ability supported
10BASE-T Half Duplex
This bit indicates the emulated link partner PHY 10BASE-T half duplex
capability.
0: 10BASE-T half duplex ability not supported
1: 10BASE-T half duplex ability supported
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13.35 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 13.36 The emulated link partner does not support next page, always instantly sends its link code
Note 13.37 The emulated link partner’s asymmetric/symmetric pause ability is based upon the values
Table 13.6 Emulated Link Partner Pause Flow Control Ability Default Values
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
word, never sends a fault, and does not support 100BASE-T4.
of the
Advertisement Register
accommodates the request of the Virtual PHY, as shown in
The link partner pause ability bits are determined when Auto-Negotiation is complete.
Changing the
have no affect until the Auto-Negotiation process is re-run. If the local device advertises
both Symmetric and Asymmetric pause, the result is determined based on the
FD_FC_strap_0
If
7.3.1, "Virtual PHY Auto-Negotiation," on page 102
(REGISTER 4.10)
SYMMETRIC
FD_FC_strap_0
PAUSE
VPHY
Asymmetric Pause
0
1
0
1
1
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)
DESCRIPTION
configuration strap. This allows the user the choice of network emulation.
(REGISTER 4.11)
= 1, then the result is Symmetrical, else Asymmetrical. See
ASYMMETRIC
DATASHEET
PAUSE
VPHY
0
0
1
1
1
and
(VPHY_AN_ADV). Thus the emulated link partner always
179
Symmetric Pause
FD_FC_strap_0
0
1
x
x
x
bits of the
for additional information.
(REGISTER 5.10)
LINK PARTNER
SYMMETRIC
Table
Virtual PHY Auto-Negotiation
PAUSE
0
1
1
0
1
TYPE
13.6.
RO
RO
RO
RO
Revision 1.4 (07-07-10)
(REGISTER 5.11)
LINK PARTNER
Note 13.38
Note 13.38
Note 13.38
DEFAULT
ASYMMETRIC
00001b
PAUSE
Section
0
0
1
1
1
will