LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 183

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
BITS
4:2
1
0
Current Speed/Duplex Indication
This field indicates the current speed and duplex of the Virtual PHY link.
RESERVED
SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
Note:
Note 13.44 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 13.45 The default value of this field is determined via the
Note 13.46 The default value of this field is determined via the
Note 13.47 The default value of this field is determined via the
Note 13.48 The default value of this field is determined via the
Note 13.49 The default value of this field is the result of the Auto-Negotiation process if the
Note 13.50 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via
Note 13.51 The default value of this field is determined via the
[4]
0
0
0
0
1
1
1
1
This bit is used when Port 0 is in MII PHY mode. It is not usable
in RMII PHY or MII MAC modes.
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
strap. Refer to
straps. Refer to
information.
strap. Refer to
strap. Refer to
N e g o t i a t i o n ( V P H Y _ A N )
(VPHY_BASIC_CTRL)
(VPHY_SPEED_SEL_LSB)
VPHY_BASIC_CTRL register. Refer to
page 102
the
t h e
(VPHY_BASIC_CTRL)
configuration strap. Refer to
additional information.
[3]
0
0
1
1
0
0
1
1
Reset Control Register
R e s e t ( V P H Y _ R S T )
for information on the Auto-Negotiation determination process of the Virtual PHY.
[2]
Section 4.2.4, "Configuration Straps," on page 45
Section 4.2.4, "Configuration Straps," on page 45
Section 4.2.4, "Configuration Straps," on page 45
0
1
0
1
0
1
0
1
DESCRIPTION
Section 4.2.4, "Configuration Straps," on page 45
DATASHEET
is set.
is set. Otherwise, this field reflects the
100/200Mbps
100/200Mbps
(RESET_CTL). The NASR designation is only applicable when
10Mbps
10Mbps
Speed
and
183
b i t o f t h e
b i t o f t h e
Section 4.2.4, "Configuration Straps," on page 45
Duplex Mode (VPHY_DUPLEX)
RESERVED
RESERVED
RESERVED
RESERVED
Section 7.3.1, "Virtual PHY Auto-Negotiation," on
Vi r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
half-duplex
half-duplex
full-duplex
full-duplex
Duplex
turbo_mii_enable_strap_0
P0_clock_strength_strap
P0_rmii_clock_dir_strap
P0_mode_strap[1:0]
SQE_test_disable_strap_0
Note 13.50
for additional information.
for additional information.
for additional information.
NASR
TYPE
R/W
RO
RO
Revision 1.4 (07-07-10)
Speed Select LSB
bit settings of the
for additional
Note 13.49
Note 13.51
DEFAULT
configuration
configuration
configuration
configuration
-
Auto-
for