LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 104

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
7.3.1.3
7.3.2
7.3.2.1
7.3.3
7.3.3.1
Virtual PHY Pause Flow Control
The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs
advertised pause flow control abilities are set via the
the
PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the emulated
link partner. The default values of these bits are as shown in
Negotiation Advertisement Register (VPHY_AN_ADV)," on page
The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised
pause flow control abilities of the Virtual PHY as indicated in the
Pause
emulated link partner always accommodates the asymmetric/symmetric pause ability settings
requested by the Virtual PHY, as shown in
Ability Default Values,” on page
The pause flow control settings may also be manually set via the
(MANUAL_FC_0). This register allows the Switch Fabric Port 0 flow control settings to be manually
set when auto-negotiation is disabled or the
(MANUAL_FC_0)
monitored via this register. The flow control values in the
Register (VPHY_AN_ADV)
Section 6.2.3, "Flow Control Enable Logic," on page 62
Virtual PHY in MAC Mode
In the MAC mode of operation, an external PHY is connected to the MII interface of the device.
Because there is an external PHY present, the Virtual PHY is not needed for external configuration.
However, the Port 0 Switch Fabric MAC still requires the proper duplex setting. Therefore, in MAC
mode, if the
(VPHY_BASIC_CTRL)
configuration strap. If these signals are equal, the Port 0 Switch Fabric MAC is configured for full-
duplex, otherwise it is set for half-duplex. The P0_DUPLEX pin is typically connected to the duplex
indication of the external PHY. The duplex is not latched since the auto-negotiation process is not used.
The duplex can be manually selected by clearing the
t h e
(VPHY_BASIC_CTRL).
Note: In MAC mode, the Virtual PHY registers are accessible through their memory mapped registers
Full-Duplex Flow Control
In the MAC mode of operation, the Virtual PHY is not applicable. Therefore, full-duplex flow control
should be controlled manually by the host via the
(MANUAL_FC_0), based on the external PHYs auto-negotiation results.
Virtual PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY
supports two block specific resets. These are is discussed in the following sections. For detailed
information on all resets, refer to
Virtual PHY Software Reset via RESET_CTL
The Virtual PHY can be reset via the
Reset (VPHY_RST)
Virtual PHY Auto-Negotiation Advertisement Register
D u p l e x M o d e ( V P H Y _ D U P L E X )
bits of the
via the SMI or I
accessible through MII management.
Auto-Negotiation (VPHY_AN)
Virtual PHY Auto-Negotiation Advertisement Register
bit is set. The currently enabled duplex and flow control settings can also be
bit. This bit is self clearing after approximately 102uS.
is set, the duplex is based on the P0_DUPLEX pin and
2
C serial management interfaces only. The Virtual PHY registers are not
are not affected by the values of the manual flow control register. Refer to
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
179.
Section 4.2, "Resets," on page
DATASHEET
Reset Control Register (RESET_CTL)
104
b i t i n t h e
Table 13.6, “Emulated Link Partner Pause Flow Control
bit of the
Port 0 Full-Duplex Manual Flow Control Select
Symmetric Pause
Auto-Negotiation (VPHY_AN)
for additional information.
Vi r t u a l P H Y B a s i c C o n t r o l R e g i s t e r
Virtual PHY Auto-Negotiation Advertisement
Port 0 Manual Flow Control Register
(VPHY_AN_ADV). This allows the Virtual
Virtual PHY Basic Control Register
Section 13.2.6.5, "Virtual PHY Auto-
176.
42.
Port 0 Manual Flow Control Register
Symmetric Pause
and
(VPHY_AN_ADV). Thus, the
by setting the
Asymmetric Pause
SMSC LAN9303/LAN9303i
duplex_pol_strap_0
bit and controlling
and
Asymmetric
Virtual PHY
Datasheet
bits of