LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 143

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.2.1.3
25:20
18:13
BITS
11:0
31
30
29
28
27
26
19
12
Software Interrupt Enable (SW_INT_EN)
Device Ready Enable (READY_EN)
RESERVED
Switch Fabric Interrupt Event Enable (SWITCH_INT_EN)
Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)
Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)
RESERVED
GP Timer Interrupt Enable (GPT_INT_EN)
RESERVED
GPIO Interrupt Event Enable (GPIO_EN)
RESERVED
Interrupt Enable Register (INT_EN)
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables
the corresponding interrupt as a source for IRQ. Bits in the
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register (with the exception of
descriptions of each interrupt, refer to the
layout of this register.
Offset:
05Ch
DESCRIPTION
DATASHEET
143
Interrupt Status Register (INT_STS)
Size:
Software Interrupt Enable
Interrupt Status Register (INT_STS)
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
bits, which mimic the
(SW_INT_EN)). For
Revision 1.4 (07-07-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
-
-
-
-
register