LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 193

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.3.2.1
BITS
15
14
13
12
11
10
Reset (PHY_RST)
When set, this bit resets all the Port x PHY registers to their default state,
except those marked as NASR type. This bit is self clearing.
0: Normal operation
1: Reset
Loopback (PHY_LOOPBACK)
This bit enables/disables the loopback mode. When enabled, transmissions
from the Switch Fabric are not sent to network. Instead, they are looped
back into the Switch Fabric.
Note:
0: Loopback mode disabled (normal operation)
1: Loopback mode enabled
Speed Select LSB (PHY_SPEED_SEL_LSB)
This bit is used to set the speed of the Port x PHY when the
Negotiation (PHY_AN)
0: 10 Mbps
1: 100 Mbps
Auto-Negotiation (PHY_AN)
This bit enables/disables Auto-Negotiation. When enabled, the
LSB (PHY_SPEED_SEL_LSB)
overridden.
0: Auto-Negotiation disabled
1: Auto-Negotiation enabled
Power Down (PHY_PWR_DWN)
This bit controls the power down mode of the Port x PHY. After this bit is
cleared the PHY may auto-negotiate with it’s partner station. This process
can take up to a few seconds to complete. Once Auto-Negotiation is
complete, the
Register (PHY_BASIC_STATUS_x)
Note:
0: Normal operation
1: General power down mode
RESERVED
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
This read/write register is used to configure the Port x PHY.
Note: This register is re-written in its entirety by the EEPROM Loader following the release of reset
If loopback is enabled during half-duplex operation, then the
Enable Receive Own Transmit
Configuration Register (MAC_RX_CFG_x)
specified port. Otherwise, the Switch Fabric will ignore receive
activity when transmitting in half-duplex mode.
The PHY_AN bit of this register must be cleared before setting this
bit.
or a RELOAD command. Refer to
information.
Index (decimal): 0
Auto-Negotiation Complete
bit is disabled.
DESCRIPTION
and
will be set.
Duplex Mode (PHY_DUPLEX)
DATASHEET
bit in the
bit of the
193
Section 8.4, "EEPROM Loader," on page 113
Port x MAC Receive
Size:
Port x PHY Basic Status
must be set for the
Speed Select
Auto-
16 bits
bits are
TYPE
R/W
R/W
R/W
R/W
R/W
RO
SC
Revision 1.4 (07-07-10)
Note 13.55
Note 13.56
DEFAULT
for additional
0b
0b
0b
-