ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 99

• Manufacturer Part Number: ISP1583BSUM
• Description: IC USB PERIPH CONTROLLER 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1886-2; ISP1583BS,518; ISP1583BS-T

NXP Semiconductors
25. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.13.1
8.13.2
8.14
8.15
8.16
8.16.1
8.16.2
8.16.3
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.4.1
ISP1583_7
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . 12
Register description . . . . . . . . . . . . . . . . . . . . 29
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
DMA interface, DMA handler and
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hi-Speed USB transceiver . . . . . . . . . . . . . . . 14
MMU and integrated RAM . . . . . . . . . . . . . . . 14
Microcontroller interface and
microcontroller handler . . . . . . . . . . . . . . . . . . 14
OTG SRP module . . . . . . . . . . . . . . . . . . . . . . 14
NXP high-speed transceiver . . . . . . . . . . . . . . 15
NXP Parallel Interface Engine (PIE) . . . . . . . . 15
Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 15
HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
NXP Serial Interface Engine (SIE) . . . . . . . . . 15
SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reconfiguring endpoints . . . . . . . . . . . . . . . . . 16
System controller . . . . . . . . . . . . . . . . . . . . . . 16
Modes of operation . . . . . . . . . . . . . . . . . . . . . 16
Pins status . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt output pin . . . . . . . . . . . . . . . . . . . . . 18
Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 20
V
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-sharing mode. . . . . . . . . . . . . . . . . . . . 24
Self-powered mode. . . . . . . . . . . . . . . . . . . . . 26
Bus-powered mode. . . . . . . . . . . . . . . . . . . . . 27
Register access . . . . . . . . . . . . . . . . . . . . . . . 30
Initialization registers . . . . . . . . . . . . . . . . . . . 31
Address register (address: 00h) . . . . . . . . . . . 31
Mode register (address: 0Ch) . . . . . . . . . . . . . 31
Interrupt Configuration register
(address: 10h). . . . . . . . . . . . . . . . . . . . . . . . . 33
OTG register (address: 12h) . . . . . . . . . . . . . . 34
Session Request Protocol (SRP) . . . . . . . . . . 36
BUS
sensing . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rev. 07 — 22 September 2008
9.2.5
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
10
11
12
13
13.1
13.1.1
13.1.1.1
13.1.1.2
13.1.2
13.1.2.1
13.1.2.2
13.2
13.2.1
13.2.2
13.2.3
14
15
16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 65
Recommended operating conditions . . . . . . 65
Static characteristics . . . . . . . . . . . . . . . . . . . 65
Dynamic characteristics . . . . . . . . . . . . . . . . . 67
Application information . . . . . . . . . . . . . . . . . 84
Test information. . . . . . . . . . . . . . . . . . . . . . . . 84
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 86
Interrupt Enable register (address: 14h) . . . . 36
Data flow registers . . . . . . . . . . . . . . . . . . . . . 38
Endpoint Index register (address: 2Ch) . . . . . 38
Control Function register (address: 28h) . . . . 39
Data Port register (address: 20h) . . . . . . . . . . 40
Buffer Length register (address: 1Ch) . . . . . . 41
Buffer Status register (address: 1Eh) . . . . . . . 42
Endpoint MaxPacketSize register
(address: 04h) . . . . . . . . . . . . . . . . . . . . . . . . 43
Endpoint Type register (address: 08h) . . . . . . 44
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 45
DMA Command register (address: 30h) . . . . 47
DMA Transfer Counter register (address: 34h) 49
DMA Configuration register (address: 38h) . . 50
DMA Hardware register (address: 3Ch) . . . . . 52
Task File registers (addresses: 40h to 4Fh) . . 53
DMA Interrupt Reason register (address: 50h) 56
DMA Interrupt Enable register (address: 54h) 57
DMA Endpoint register (address: 58h). . . . . . 57
DMA Strobe Timing register (address: 60h). . 58
DMA Burst Counter register (address: 64h). . 59
General registers . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt register (address: 18h). . . . . . . . . . . 59
Chip ID register (address: 70h) . . . . . . . . . . . 61
Frame Number register (address: 74h) . . . . . 62
Scratch register (address: 78h) . . . . . . . . . . . 62
Unlock Device register (address: 7Ch). . . . . . 63
Test Mode register (address: 84h) . . . . . . . . . 63
Register access timing . . . . . . . . . . . . . . . . . . 69
Generic processor mode . . . . . . . . . . . . . . . . 69
8051 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Freescale mode . . . . . . . . . . . . . . . . . . . . . . . 71
Split bus mode . . . . . . . . . . . . . . . . . . . . . . . . 73
ALE function. . . . . . . . . . . . . . . . . . . . . . . . . . 73
A0 function . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PIO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 81
MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 83
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
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