ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 33

• Manufacturer Part Number: ISP1583BSUM
• Description: IC USB PERIPH CONTROLLER 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1886-2; ISP1583BS,518; ISP1583BS-T

NXP Semiconductors
Table 24.
[1]
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Value depends on the status of the V
Mode register: bit allocation
unchanged
CLKAON
TEST2
R/W
15
R
7
0
-
-
Table 25.
Bit
15
14
13
12 to 10 -
9
8
7
6
5
4
SNDRSU
TEST1
R/W
14
R
6
0
0
-
-
Symbol
TEST2
TEST1
TEST0
DMACLKON
VBUSSTAT
CLKAON
SNDRSU
GOSUSP
SFRESET
Mode register: bit description
BUS
pin.
GOSUSP
TEST0
R/W
13
R
5
0
0
-
-
Rev. 07 — 22 September 2008
Description
This bit reflects the MODE1 pin setting. Only for test purposes.
This bit reflects the MODE0/DA1 pin setting. Only for test purposes.
This bit reflects the BUS_CONF/DA0 pin setting. Only for test purposes.
reserved
DMA Clock On:
0 — Power save mode; the DMA circuit will stop completely to save
power.
1 — Supply clock to the DMA circuit.
V
Clock Always On: Logic 1 indicates that internal clocks are always
running when in the suspend state. Logic 0 switches off the internal
oscillator and PLL when the device goes into suspend mode. The
device will consume less power if this bit is set to logic 0. The clock is
stopped about 2 ms after bit GOSUSP is set and then cleared.
Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms
upstream resume signal.
Remark: The upstream resume signal is generated 5 ms after this bit is
set to logic 0.
Go Suspend: Writing logic 1, followed by logic 0 will activate suspend
mode.
Soft Reset: Writing logic 1, followed by logic 0 will enable a
software-initiated reset to the ISP1583. A soft reset is similar to a
hardware-initiated reset (using the RESET_N pin).
BUS
SFRESET
Pin Status: This bit reflects the V
R/W
12
4
0
0
-
-
-
GLINTENA
unchanged
reserved
R/W
11
3
0
-
-
-
Hi-Speed USB peripheral controller
WKUPCS
R/W
10
2
0
0
-
-
-
BUS
pin status.
unchanged
PWRON
CLKON
DMA
R/W
R/W
9
0
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1583
VBUSSTAT
unchanged
SOFTCT
R/W
-
-
R
8
[1]
[1]
0
0
32 of 99