ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 48

• Manufacturer Part Number: ISP1583BSUM
• Description: IC USB PERIPH CONTROLLER 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1886-2; ISP1583BS,518; ISP1583BS-T

NXP Semiconductors
Table 51.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
9.4.1 DMA Command register (address: 30h)
W
7
1
1
Table 49.
Table 50.
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-stated.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activity on the DMA controller. The register is write-only: reading
it will return FFh.
Remark: The DMA bus will be in 3-state, until a DMA command is executed.
Control bits
DMA Hardware register
ENDIAN[1:0]
EOT_POL
MASTER
ACK_POL,
DREQ_POL,
WRITE_POL,
READ_POL
Control bits
DMA Configuration register
ATA_MODE
DMA_MODE[1:0]
PIO_MODE[2:0]
DMA Hardware register
MASTER
W
6
1
1
Control bits for Generic DMA transfers
Control bits for IDE-specified DMA transfers
Description
GDMA read/write
(opcode = 00h/01h)
determines whether data is
to be byte swapped or
normal; applicable only in
16-bit mode
selects polarity of the EOT
signal
set to logic 0 (slave)
selects polarity of DMA
handshake signals
Rev. 07 — 22 September 2008
W
Description
MDMA read/write (opcode = 06h/07h)
set to logic 1 (ATA transfer)
selects MDMA mode; timing are ATA(PI) compatible
selects PIO mode; timing are ATA(PI) compatible
set to logic 0
5
1
1
DMA_CMD[7:0]
W
4
1
1
W
3
1
1
MDMA (master) read/write
(opcode = 06h/07h)
determines whether data is to
be byte swapped or normal;
applicable only in 16-bit mode
input EOT is not used
set to logic 1 (master)
selects polarity of DMA
handshake signals
…continued
Hi-Speed USB peripheral controller
W
2
1
1
W
1
1
1
Table
© NXP B.V. 2008. All rights reserved.
ISP1583
Reference
Table 56
Table 58
Reference
Table 58
51) that
W
0
1
1
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