ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 64

IC USB PERIPH CONTROLLER 64HVQFN

ISP1583BSUM

Manufacturer Part Number
ISP1583BSUM
Description
IC USB PERIPH CONTROLLER 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1583BSUM

Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1886-2
ISP1583BS,518
ISP1583BS-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1583BSUM
Manufacturer:
MICRON
Quantity:
2 000
Part Number:
ISP1583BSUM
Manufacturer:
ST-ERICS
Quantity:
829
Part Number:
ISP1583BSUM
Manufacturer:
ST
0
Part Number:
ISP1583BSUM
Manufacturer:
STE
Quantity:
20 000
NXP Semiconductors
Table 90.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Unlock Device register: bit allocation
9.5.5 Unlock Device register (address: 7Ch)
9.5.6 Test Mode register (address: 84h)
15
W
W
7
Table 89.
To protect registers from getting corrupted when the ISP1583 goes into suspend, the write
operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when
the chip resumes, the Unlock Device command must first be issued to this register before
attempting to write to the rest of the registers. This is done by writing unlock code (AA37h)
to this register. The bit allocation of the Unlock Device register is given in
Table 91.
When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you
do not need to issue the Unlock command because the microprocessor is powered and
therefore, the RW_N/RD_N, DS_N/WR_N and CS_N signals maintain their states.
When bit PWRON is logic 0, the RW_N/RD_N, DS_N/WR_N and CS_N signals are
floating because the microprocessor is not powered. To protect the ISP1583 registers
from being corrupted during suspend, register write is locked when the chip goes into
suspend. Therefore, you need to issue the Unlock command to unlock the ISP1583
registers.
This 1-byte register allows the firmware to set the DP and DM pins to predetermined
states for testing purposes. The bit allocation is given in
Remark: Only one bit can be set at a time. Either bit FORCEHS or FORCEFS must be set
to logic 1 at a time. Of the four bits PRBS, KSTATE, JSTATE and SE0_NAK only one bit
must be set at a time. This must be implemented for the Hi-Speed USB logo compliance
testing. To exit test mode, power cycle is required.
Bit
15 to 8
7 to 0
Bit
15 to 0
14
W
W
6
Scratch register: bit description
Unlock Device register: bit description
Symbol
SFIRH[7:0]
SFIRL[7:0]
Symbol
ULCODE[15:0]
13
W
W
5
Rev. 07 — 22 September 2008
Description
Scratch firmware information register (higher byte)
Scratch firmware information register (lower byte)
Description
Unlock Code: Writing data AA37h unlocks internal registers and
FIFOs for writing, following a resume.
ULCODE[15:8] = AAh
ULCODE[7:0] = 37h
12
W
W
4
not applicable
not applicable
not applicable
not applicable
11
W
W
3
Hi-Speed USB peripheral controller
Table
10
W
W
2
92.
W
W
9
1
© NXP B.V. 2008. All rights reserved.
ISP1583
Table
90.
W
W
8
0
63 of 99

Related parts for ISP1583BSUM