ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 31

• Manufacturer Part Number: ISP1583BSUM
• Description: IC USB PERIPH CONTROLLER 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1886-2; ISP1583BS,518; ISP1583BS-T

NXP Semiconductors
Table 21.
ISP1583_7
Product data sheet
Name
Task File 1F0
Task File 1F1
Task File 1F2
Task File 1F3
Task File 1F4
Task File 1F5
Task File 1F6
Task File 1F7
Task File 3F6
Task File 3F7
DMA Interrupt Reason
DMA Interrupt Enable
DMA Endpoint
DMA Strobe Timing
DMA Burst Counter
General registers
Interrupt
Chip ID
Frame Number
Scratch
Unlock Device
Test Mode
Register overview
9.1 Register access
Register access depends on the bus width used:
Endpoint specific registers are indexed using the Endpoint Index register. The target
endpoint must be selected before accessing the following registers:
•
•
Destination
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
ATAPI peripheral
DMA controller
DMA controller
DMA controller
DMA controller
DMA controller
device
device
device
device
device
PHY
8-bit bus: multi-byte registers are accessed lower byte (LSByte) first
16-bit bus: for single-byte registers, the upper byte (MSByte) must be ignored
…continued
Rev. 07 — 22 September 2008
Address Description
40h
48h
49h
4Ah
4Bh
4Ch
4Dh
44h
4Eh
4Fh
50h
54h
58h
60h
64h
18h
70h
74h
78h
7Ch
84h
single address word register: byte 0
(lower byte) is accessed first
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access
IDE device access (write only; reading
returns FFh)
IDE device access
IDE device access
shows reason (source) for DMA
interrupt
enables DMA interrupt sources
selects endpoint FIFO, data flow
direction
strobe duration in MDMA mode
DMA burst length
shows interrupt sources
product ID code and hardware version 3
last successfully received
Start-Of-Frame: lower byte (byte 0) is
accessed first
allows save or restore of firmware
status during suspend
re-enables register write access after
suspend
direct setting of the DP and DM
states, internal transceiver test (PHY)
Hi-Speed USB peripheral controller
Size
(bytes)
2
1
1
1
1
1
1
1
1
1
2
2
1
1
2
4
2
2
2
1
© NXP B.V. 2008. All rights reserved.
ISP1583
Reference
Section 9.4.5
on page 53
Section 9.4.6
on page 56
Section 9.4.7
on page 57
Section 9.4.8
on page 57
Section 9.4.9
on page 58
Section 9.4.10
on page 59
Section 9.5.1
on page 59
Section 9.5.2
on page 61
Section 9.5.3
on page 62
Section 9.5.4
on page 62
Section 9.5.5
on page 63
Section 9.5.6
on page 63
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