MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 98

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
4.7.1 Instruction Cache
The IU uses the instruction cache to store instruction prefetches as it requests them.
Instruction prefetches are normally requested from sequential memory locations except
when a change of program flow occurs (e.g., a branch taken) or when an instruction that
can modify the status register (SR) is executed, in which case the instruction pipe is
automatically flushed and refilled. The instruction cache supports a line-based protocol
that allows individual cache lines to be in either the invalid or valid states.
For instruction prefetch requests that hit in the cache, the half-line selected by physical
address bit 3 is multiplexed onto the internal instruction data bus. When an access misses
in the cache, the cache controller requests the line containing the required data from
memory and places it in the cache. If available, an invalid line is selected and updated
with the tag and data from memory. The line state then changes from invalid to valid by
setting the V-bit. If all lines in the set are already valid, a pseudo-random replacement
algorithm is used to select one of the four cache lines replacing the tag and data contents
of the line with the new line information. Figure 4-5 illustrates the instruction-cache line
state transitions resulting from processor and snoop controller accesses. Transitions are
labeled with a capital letter, indicating the previous state, followed by a number indicating
the specific case listed in Table 4-3.
I3–CINV/CPUSH
V1–CPU READ MISS
V2–CPU READ HIT
I1-CPU READ MISS
INVALID
VALID
V3–CINV/CPUSH
V5–SNOOP READ HIT
V6–SNOOP WRITE HIT
Figure 4-5. Instruction-Cache Line State Diagram
4-14
M68040 USER'S MANUAL
MOTOROLA
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