MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 107

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

applications. Refer to Section 7 Bus Operation for detailed information about the
relationship of the address bus to bus operation and the multiplexed bus mode. Refer to
Appendix A MC68LC040 and Appendix B MC68EC040 for details concerning the CDIS
level and multiplexed bus mode.
5.2 DATA BUS (D31–D0)
These three-state bidirectional signals provide the general-purpose data path between the
M68040 and all other devices. The data bus can transfer 8, 16, or 32 bits of data per bus
transfer. During a burst transfer, the data lines are time-multiplexed to carry all 128 bits of
the burst request using four 32-bit transfers.
The level on CDIS can select a multiplexed bus mode during processor reset, which
allows the data bus and address bus to be physically tied together for multiplexed bus
applications. The level on MDIS can select a data latch mode during processor reset,
which allows the memory interface to specify when the processor should latch input data
through the DLE signal. Section 7 Bus Operation provides detailed information about the
relationship of the data bus to bus operation, the multiplexed bus mode, and the data latch
mode. Refer to Appendix A MC68LC040 and Appendix B MC68EC040 for details
concerning the CDIS level and multiplexed bus mode.
5.3 TRANSFER ATTRIBUTE SIGNALS
The following paragraphs describe the transfer attribute signals, which provide additional
information about the bus transfer. Refer to Section 7 Bus Operation for detailed
information about the relationship of the transfer attribute signals to bus operation.
5.3.1 Transfer Type (TT1, TT0)
The processor drives these three-state bidirectional signals to indicate the type of access
for the current bus transfer. During bus transfers by an alternate bus master, the
processor samples these signals to determine if it should snoop the transfer; only normal
and MOVE16 accesses can be snooped. Table 5-2 lists the definition of the transfer-type
encoding. The acknowledge access (TT1 = 1 and TT0 = 1) is used for both interrupt and
breakpoint acknowledge transfers, and for LPSTOP broadcast cycles on the MC68040V
and MC68EC040V.
MOTOROLA
TT1
0
0
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-2. Transfer-Type Encoding
TT0
0
1
0
1
Go to: www.freescale.com
M68040 USER’S MANUAL
Normal Access
MOVE16 Access
Alternate Logical Function Code Access
Acknowledge Access
Transfer Type
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