MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 379

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

B.2 JTAG SCAN (JS1–JS0)
The MC68040 MDIS and DLE pin names have been changed to JS1 and JS0 respectively.
During normal operation, the JS1 and JS0 pin cannot float, they must be tied to GND or Vcc
directly or through a resistor. During board testing, these pins retain the functionality of the
JTAG scan of the MC68040 for compatibility purposes. Refer to Section 6 IEEE 1149.1A
MOTOROLA
• PTEST and PFLUSH instructions cause an indeterminate result (i.e., an undetermined
• The MC68EC040 does not contain an FPU which causes unimplemented floating-point
• The DLE and MDIS pin names have been changed to JS0 and JS1, respectively.
• The MC68EC040 does not implement the DLE mode, multiplexed, or output buffer im-
number of bus cycles); the user should not execute them on the MC68EC040.
exceptions to occur using a new stack frame format.
pedance selection modes of operation. The MC68EC040 implements only the small
output buffer mode of operation. All timing and drive capabilities of the MC68EC040 are
equivalent to those of the MC68040 in the small buffer mode of operation.
31
31
REGISTERS
REGISTERS
ADDRESS
DATA
Figure B-2. MC68EC040 Programming Model
Freescale Semiconductor, Inc.
For More Information On This Product,
USER PROGRAMMING MODEL
(CCR)
SUPERVISOR PROGRAMMING MODEL
0
0
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7/USP
PC
CCR
A7’/ISP
A7”/MSP
SR
VBR
SFC
DFC
CACR
URP
SRP
TC
DTT0
DTT1
ITT0
ITT1
MMUSR
Go to: www.freescale.com
M68040 USER’S MANUAL
USER STACK POINTER
PROGRAM COUNTER
CONDITIONAL CODE REGISTER
INTERRUPT STACK POINTER
MASTER STACK POINTER
STATUS REGISTER
VECTOR BASE REGISTER
SOURCE FUNCTION CODE
DESTINATION FUNCTION CODE
CACHE CONTROL REGISTER
USER ROOT POINTER REGISTER
SUPERVISOR ROOT POINTER REGISTER
TRANSLATION CONTROL REGISTER
DATA TRANSPARENT TRANSLATION REGISTER 0
DATA TRANSPARENT TRANSLATION REGISTER 1
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1
MMU STATUS REGISTER
MC68EC040
REV2.3 (01/31/2000)
B-3