MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 208

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

should not exceed V
BCLKS before being used and must meet the specified setup and hold times to BCLK
(specifications #51 and #52 in Section 11 MC68040 Electrical and Thermal
Characteristics) only if recognition by a specific BCLK rising edge is required. MI is
asserted while the M68040 is in reset.
Once RSTI negates, the processor is internally held in reset for another 128 clock cycles.
During the reset period, all signals that can be, are three-stated, and the rest are driven to
their inactive state. Once the internal reset signal negates, all bus signals continue to
remain in a high-impedance state until the processor is granted the bus. Afterwards, the
first bus cycle for reset exception processing begins. In Figure 7-44 the processor
assumes implicit bus ownership before the first bus cycle begins. The levels on CDIS
MDIS, and IPL2–IPL0 are used to selectively enable the special modes of operation when
RSTI is negated. These signals should be driven to their normal levels before the end of
the 128-clock internal reset period.
7-66
CDIS, MDIS,
IPL2–IPL0
SIGNALS
V CC
BCLK
RSTI
+5 V
BUS
TIP
0 V
BR
BG
TS
BB
MI
Undefined
CC
Figure 7-44. Initial Power-On Reset Timing
Freescale Semiconductor, Inc.
while it is ramping up. RSTI is internally synchronized for two
For More Information On This Product,
CLOCKS
t 10
>
M68040 USER’S MANUAL
Go to: www.freescale.com
CLOCKS
2
CLOCKS
128
MOTOROLA
,