MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 22

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
SECTION 1
INTRODUCTION
The MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively
called M68040) are Motorola’s third generation of M68000-compatible, high-performance,
32-bit microprocessors. All five devices are virtual memory microprocessors employing
multiple concurrent execution units and a highly integrated architecture that provides very
high performance in a monolithic HCMOS device. They integrate an MC68030-compatible
integer unit (IU) and two independent caches. The MC68040, MC68040V, and
MC68LC040 contain dual, independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction
and data caches. The MC68040 contains an MC68881/MC68882-compatible floating-
point unit (FPU). The use of multiple independent execution pipelines, multiple internal
buses, and a full internal Harvard architecture, including separate physical caches for both
instruction and data accesses, achieves a high degree of instruction execution parallelism
on all three processors. The on-chip bus snoop logic, which directly supports cache
coherency in multimaster applications, enhances cache functionality.
The M68040 family is user object-code compatible with previous M68000 family members
and is specifically optimized to reduce the execution time of compiler-generated code. All
five processors implement Motorola’s latest HCMOS technology, providing an ideal
balance between speed, power, and physical device size.
1.1 DIFFERENCES
Because the functionality of individual M68040 family members are similar, this manual is
organized so that the reader will take the following differences into account while reading
the rest of this manual. Unless otherwise noted, all references to M68040, with the
exception of the differences outlined below, will apply to the MC68040, MC68040V,
MC68LC040, MC68EC040, and MC68EC040V. The following paragraphs describe the
differences of MC68040V, MC68LC040, MC68EC040, and the MC68EC040V from the
MC68040.
1.1.1 MC68040V and MC68LC040
The MC68040V and MC68LC040 are derivatives of the MC68040. They implement the
same IU and MMU as the MC68040, but have no FPU. The MC68LC040 is pin compatible
with the MC68040. The MC68040V is not pin compatible with the MC68040 and contains
some additional features. The following differences exist between the MC68040V,
MC68LC040, and MC68040:
MOTOROLA
M68040 USER’S MANUAL
1- 1
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