MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 250

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Many users elect to disable traps for all or part of the floating-point exception classes. The
AEXC byte makes it unnecessary to poll the EXC byte after each floating-point instruction.
At the end of most operations (FMOVEM and FMOVE excluded), the bits in the EXC byte
are logically combined to form an AEXC value that is logically ORed into the existing
AEXC byte. This operation creates sticky floating-point exception bits in the AEXC byte
that the user needs to poll only once (i.e., at the end of a series of floating-point
operations). A sticky bit is one that remains set until the user clears it.
Setting or clearing the AEXC bits neither causes nor prevents an exception. The following
equations show the comparative relationship between the EXC byte and AEXC byte.
Comparing the current value in the AEXC bit with a combination of bits in the EXC byte
derives a new value in the corresponding AEXC bit. These equations apply to setting the
AEXC bits at the end of each operation affecting the AEXC byte:
9.2.4 Floating-Point Instruction Address Register (FPIAR)
For the subset of the floating-point instructions that generate exception traps, the FPU
loads the 32-bit FPIAR with the logical address of the instruction before executing the
instruction. Because the IU can execute instructions while the FPU executes floating-point
instructions and, the FPU can concurrently execute two floating-point instructions the PC
value stacked by the MC68040 in response to a floating-point exception handler cannot
point to the offending instruction. Therefore, a floating-point exception handler uses the
address in the FPIAR to locate a floating-point instruction that has caused an exception.
Since the FMOVE to/from the FPCR, FPSR, or FPIAR and FMOVEM instructions cannot
generate floating-point exceptions, these instructions do not modify the FPIAR. However,
9-6
IOP
7
OVFL
6
IOP
OVFL
UNFL
DZ
INEX
AEXC Bit
Figure 9-6. FPSR Accrued Exception Byte
New
Freescale Semiconductor, Inc.
UNFL
For More Information On This Product,
5
= Old AEXC
DZ
M68040 USER’S MANUAL
4
Go to: www.freescale.com
= IOP
= OVFL
= UNFL
= DZ
= INEX
Bit
INEX
3
V
V
V
V
V
V
2
EXC Bits
(SNAN V OPERR)
(OVFL)
(UNFL
(DZ)
(INEX1 V INEX2 V OVFL)
1
INEX2)
0
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
INVALID OPERATION
INEXACT
MOTOROLA