MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 242

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

After the fault is corrected, any pending write-backs on the stack frame must be
completed. The write-back status fields should be checked for possible write-backs, which
the exception handler should complete in the following order: write-back 1, write-back 2,
and write-back 3. For a push fault, the push must be completed first, followed by two
potential write-backs. Completion of write-back 1 should not generate another access
error since this write-back corresponds to the faulted access that has been corrected by
the handler. However, write-backs 2 and 3 can cause another bus error exception when
the handler attempts to write to memory and should be checked before attempting the
write to prevent nesting of exceptions if required by the operating system. The following
general bus fault examples indicate the resulting contents of the access error stack frame
fields:
MOTOROLA
1. All Read Access Errors (SSW–RW = $1, TT = $0, TM = $1 or $5)—The FA field
2. Cache Push Physical Bus Error (SSW–RW = $0, TT = $0, TM = $0)—The assertion
3. Normal Write Physical Bus Error (SSW–RW = $0, TT = $0, TM = $1 or $5)—The
4. MOVE16 Write Physical Bus Error (SSW–RW = $0, TT = $1)—The assertion of TEA
5. Page Fault (SSW–RW = $0, WB1S–V = $0)—The FA field contains the physical
contains the logical address of the fault. The WB1S and WB2S fields are zero, and
only WB3S can indicate an additional write-back.
of TEA causes this error when a cache push bus cycle is in progress. The FA field
contains the physical address of the fault, and the WB1S field is ignored. All four
long words of the data for a push are contained in LW3–LW0 regardless of the size
of the transfer. The size of the transfer is indicated in the SIZE field of the SSW and
can be either a line or long word. If a line is indicated, all four long words need to be
pushed out. If a long word is indicated, all four long words can be written out, or bits
3 and 2 of the FA field can be evaluated to indicate which long words need to be
written out to memory ($3, $2, $1, and $0 indicate LW3, LW2, LW1, and LW0,
respectively). The WB2S and WB3S fields indicate up to two additional write-backs.
If WB2S is valid and if it indicates a MOVE16 instruction, no data should be written
out for that write-back slot.
assertion of TEA causes this error when a normal write bus cycle is in progress. The
FA field contains the logical address of the fault, and the WB1S field indicates that it
is valid. The FA and WB1A are equivalent. The WB2S and WB3S fields indicate up
to two additional write-backs.
causes this error during the write portion of a MOVE16 instruction. The FA field
contains the logical address of the fault, and the WB1S field indicates that it is valid.
All four long words are contained in LW3–LW0 and must be written out before using
FA. Software must ensure that address bits 1 and 0 are both clear if regular move
instruction are to be used to write out to the destination.
address of the faulted instruction, WB1S = 0, and WB2S indicates that it is valid.
Only WB3S can indicate an additional write-back. If WB2S indicates a MOVE16
instruction and if the MOVE16 instruction is used to read from a peripheral that
cannot tolerate double reads, then software must write the data contained in PD3–
PD0 out to memory and increment the stacked PC to take it beyond the MOVE16
instruction that caused the page fault. Otherwise, if the MOVE16 instruction is
allowed to be restarted, another read from the peripheral would occur. If double
reads can be tolerated, simply do no write-backs and allow instruction to restart. This
is the only case in which the action to be taken depends on whether or not a double
read can be tolerated.
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