MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 195

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

how the LOCKE signal can be used to end a locked sequence and to yield the bus one
bus cycle earlier than is normally possible. Figure 7-35 illustrates the state diagram of a
hypothetical external arbiter design.
Assuming that processor 1 currently owns the bus, the external arbiter is in state A. If
processor 2 asserts BR2, then processor 1 behaves in one of three ways:
MOTOROLA
1. If processor 1 is currently in the middle of a nonlocked bus access, then the external
2. If processor 1 is currently in the middle of a locked bus access, then the external
3. If processor 1 is in one of the three boundary conditions, then the external arbiter
BR2
NOTES:
arbiter proceeds to state B, in which BG1 is negated and BG2 is asserted. The
external arbiter then proceeds to state C only when BB is negated, signifying the end
of the bus cycle.
arbiter stays in state A until LOCKE is asserted. Once LOCKE is asserted, the
external arbiter enters state B, in which BG1 is negated and BG2 is asserted. The
external arbiter proceeds to state C once BB is negated, signifying the end of the
bus cycle.
proceeds to state B. During state B, the external arbiter checks for the possibility of a
newly initiated locked bus access. If it detects a locked bus cycle, it returns the bus
to processor 1 by entering state A. Note that even though processor 1 recognizes
BG1 is asserted, it does not take the bus because processor 1 asserts BB whenever
the boundary condition results in processor 1 performing another bus cycle. The
external arbiter stays in state A until LOCKE is asserted, then proceeds to state B to
1.
2.
LOCK
Because this example uses two MC68040s, 1 and 2 refer to the processor and its signals.
*Indicates the signal is asserted for that device.
BB
LOCK
STATE D
BR2* V
LOCKE
Figure 7-35. Dual M68040 Fairness Arbitration State Diagram
LOCK* V BB
STATE A
LOCKE
BG1*, BG2
BG1*, BG2
Freescale Semiconductor, Inc.
BB*
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M68040 USER’S MANUAL
BR2
BB
BB
BR1
V BR2
V BR1
LOCK
LOCK
LOCK
LOCK
LOCK*
LOCKE*
LOCKE*
LOCK*
LOCKE
LOCKE
BG1, BG2*
BG1, BG2*
BB*
STATE C
BB
LOCK
BR1* V BR1
LOCK
STATE B
LOCK* V BB
LOCKE*
LOCKE
7- 53