MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 225

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.2.8 Breakpoint Instruction Exception
To use the M68040 in a hardware emulator, the processor must provide a means of
inserting breakpoints in the emulator code and performing appropriate operations at each
breakpoint. Inserting an illegal instruction at the breakpoint and detecting the illegal
instruction exception from its vector location can achieve this. However, since the VBR
allows arbitrary relocation of exception vectors, the exception address cannot reliably
identify a breakpoint. Consequently, the processor provides a breakpoint capability with a
set of breakpoint exceptions, $4848–$484F.
When the M68040 executes a breakpoint instruction, it performs a breakpoint
acknowledge cycle (read cycle) with an acknowledge transfer type and transfer modifier
value of $0. Refer to Section 7 Bus Operation for a description of the breakpoint
acknowledge cycle. After external hardware terminates the bus cycle with either TA or
TEA, the processor performs illegal instruction exception processing.
8.2.9 Interrupt Exception
When a peripheral device requires the services of the M68040 or is ready to send
information that the processor requires, it can signal the processor to take an interrupt
exception using the active-low IPL2–IPL0 signals. The three signals encode a value of 0–7
(IPL0 is the least significant bit). High levels on all three signals correspond to no interrupt
requested (level 0). Values 1–7 specify one of seven levels of interrupts, with level 7
having the highest priority. Table 8-3 lists the interrupt levels, the states of IPL2–IPL0 that
define each level, and the SR interrupt mask value that allows an interrupt at each level.
When an interrupt request has a priority higher than the value in the interrupt priority mask
of the SR (bits 10–8), the processor makes the request a pending interrupt. Priority level
7, the nonmaskable interrupt, is a special case. Level 7 interrupts cannot be masked by
the interrupt priority mask, and they are transition sensitive. The processor recognizes an
interrupt request each time the external interrupt request level changes from some lower
level to level 7, regardless of the value in the mask. Figure 8-3 shows two examples of
interrupt recognitions, one for level 6 and one for level 7. When the M68040 processes a
8-12
Interrupt Level
Requested
0
1
2
3
4
5
6
7
Table 8-3. Interrupt Levels and Mask Values
Freescale Semiconductor, Inc.
For More Information On This Product,
IPL2
High
High
High
High
Low
Low
Low
Low
Control Line Status
M68040 USER’S MANUAL
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High
High
High
High
IPL1
Low
Low
Low
Low
IPL0
High
High
High
High
Low
Low
Low
Low
Required for Recognition
No Interrupt Requested
Interrupt Mask Level
0–1
0–2
0–3
0–4
0–5
0–7
0
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