MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 286

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CMDREG1B—This field contains the command word of the exceptional floating-point
instruction for an E1 exception, which is an exception detected by the conversion unit
(CU) in the floating-point pipeline (see Figure 9-1). For FSQRT, CMDREG1B [6–0] are
mapped from $4 for the instruction to $5 in CMDREG1B. All other instructions map
directly.
CMDREG3B—This field contains the encoded instruction command word for an E3
exception, which is an exception detected by the write-back unit (WB) in the floating-point
pipeline (see Figure 9-1). Figure 9-11 details the bit mapping between CMDREG1B and
CMDREG3B. For FSQRT, bits CMDREG1B [6–0] are changed from $4 for the instruction
to $5 for CMDREG1B, and therefore map to $21 for CMDREG3B.
CU_SAVEPC—This field contains the PC for the FPU pipeline’s conversion unit.
E1—If set, this bit indicates that an exception has been detected by the conversion unit
pipeline stage. All exception types are possible. The exception handler first checks for an
E3 exception and processes it before checking and processing an E1 exception. The E1
exception is processed if the E1 bit is set. For the unimplemented instruction state frame,
the source operand’s unsupported data type is packed if the E1 bit is set.
E3—If set, this bit indicates that an exception has been detected by the WB pipeline
stage. Only OVFL, UNFL, and INEX2 exceptions on opclass 010 or 000 (register to
register and memory to register) for FADD, FSUB, FMUL, FDIV, FSQRT can occur. The
exception handler must check for and process an E3 exception first.
ETS, ETE, ETM—Collectively, these fields are referred to as the ETEMP register and
normally contain the source operand converted to extended precision. If the instruction
specifies a packed decimal real source, bits 63–0 of the operand reside in ETM [63–00],
and the ETS and ETE fields are undefined.
FPIARCU—This field contains the instruction address register for the FPU pipeline’s
conversion unit.
9-42
Figure 9-11. Mapping of Command Bits for CMDREG3B Field
CMDREG3B
CMDREG1B
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SRC
(Rx)
10 9
10 9
0
DST
DST
(Ry)
(Ry)
7 6
7 6
CMD
CMD
0
0
MOTOROLA