ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 70

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Apparent Energy Pulse Output
All the ADE7566/ADE7569/ADE7166/ADE7169 circuitry has a
pulse output whose frequency is proportional to apparent
power (see the Energy-to-Frequency Conversion section). This
pulse frequency output uses the calibrated signal after VAGAIN.
This output can also be used to output a pulse whose frequency
is proportional to I
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 79.
Line Apparent Energy Accumulation
The ADE7566/ADE7569/ADE7166/ADE7169 are designed
with a special apparent energy accumulation mode that
simplifies the calibration process. By using the on-chip, zero-
crossing detection, the ADE7566/ADE7569/ADE7166/ ADE7169
accumulate the apparent power signal in the LVAHR register for
an integral number of half cycles, as shown in Figure 77. The line
apparent energy accumulation mode is always active.
The number of half-line cycles is specified in the LINCYC
register, which is an unsigned 16-bit register. The ADE7566/
ADE7569/ADE7166/ADE7169 can accumulate apparent power
for up to 65,535 combined half cycles. Because the apparent
power is integrated on the same integral number of line cycles
as the line active register and reactive energy register, these
values can easily be compared. The energies are calculated more
accurately because of this precise timing control and provide all
the information needed for reactive power and power factor
calculation.
At the end of an energy calibration cycle, the CYCEND flag in
the Interrupt Status 3 SFR (MIRQSTH, 0xDE) is set. If the
CYCEND enable bit in the Interrupt Enable 3 SFR (MIRQENH,
0xDB) is enabled, the 8052 core has a pending ADE interrupt.
As for LWATTHR, when a new half-line cycles is written
in LINCYC register, the LVAHR register is reset and a new
accumulation start at the next zero crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
VOLTAGE CHANNEL
rms
.
FROM
ADC
LPF1
APPARENT POWER
ZERO-CROSSING
DETECTION
Figure 77. Line Cycle Apparent Energy Accumulation
or I
rms
VADIV[7:0]
%
Rev. A | Page 70 of 144
LINCYC[15:0]
CALIBR ATION
CONTROL
+
+
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
Apparent Power No-Load Detection
The ADE7566/ADE7569/ADE7166/ADE7169 include a no-
load threshold feature on the apparent power that eliminates any
creep effects in the meter. The ADE7566/ADE7569/ADE7166/
ADE7169 accomplish this by not accumulating energy if the
multiplier output is below the no-load threshold. When the
apparent power is below the no-load threshold, the
VANOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL,
0xDC) is set. If the VANOLOAD bit is set in the Interrupt
Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
APNOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no-load threshold level is selectable by setting the
VANOLOAD bits in the NLMODE register (0x0E). Setting
these bits to 0b00 disables the no-load detection and setting
them to 0b01, 0b10, or 0b11 sets the no-load detection
threshold to 0.030%, 0.015%, and 0.0075% of the full-scale
output frequency of the multiplier, respectively.
This no-load threshold can also be applied to the I
output when selected. In this case, the level of no-load threshold
is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the
energy meter, the ADE7566/ADE7569/ADE7166/ADE7169 is
capable of accumulating the ampere-hour instead of apparent
power into the VAHR, RVAHR, and LVAHR. When Bit 3
(VARMSCFCON) of the MODE2 register (0x0C) is set, the VAHR,
RVAHR, and LVAHR, and the input for the digital-to-frequency
converter accumulate I
signal processing and calibration registers available for apparent
power and energy accumulation remain the same when ampere-
hour accumulation is selected. However, the scaling difference
between I
for gain calibration in the VAGAIN, VADIV, CFxNUM, and
CFxDEN registers.
48
23
LVAHR[23:0]
rms
and apparent power requires independent values
0
rms
instead of apparent power. All the
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
0
rms
pulse