ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 122

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Table 133. Serial Port Buffer SFR (SBUF, 0x99)
Bit
7 to 0
Table 134. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E)
Bit
7
6
5
4, 3
2, 1, 0
Table 135. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)
Bit
7
6
5
4
3
2
1
0
Mnemonic
OWE
FE
BE
SBTH1, SBTH0
DIV2, DIV1, DIV0
Mnemonic
UARTBAUDEN
SBAUDF.5
SBAUDF.4
SBAUDF.3
SBAUDF.2
SBAUDF.1
SBAUDF.0
Mnemonic
SBUF
Default
0
0
0
0
0
0
0
Default
0
0
0
0
0
Description
Overwrite Error. This bit is set when new data is received and RI = 1. It indicates that SBUF was not
read before the next character was transferred in, causing the prior SBUF data to be lost. Write a 0 to
this bit to clear it.
Frame Error. This bit is set when the received frame did not have a valid stop bit. This bit is read only
and updated every time a frame is received.
Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission
frame, which is the time required for a start bit, 8 data bits, a parity bit, and half a stop bit. This bit is
updated every time a frame is received.
Extended divider ratio for baud rate setting as shown in Table 136.
Binary Divider. See Table 136.
DIV[2:0]
000
001
010
011
100
101
110
111
Description
UART Baud Rate Enable. Set to enable UART timer to generate the baud rate.
When set, PCON.7 (SMOD), T2CON.4 (TCLK), and T2CON.5 (RCLK) are ignored.
Cleared to let the baud rate be generated as per a standard 8052.
Not Implemented, Write Don’t Care.
UART Timer Fractional Divider Bit 5.
UART Timer Fractional Divider Bit 4.
UART Timer Fractional Divider Bit 3.
UART Timer Fractional Divider Bit 2.
UART Timer Fractional Divider Bit 1.
UART Timer Fractional Divider Bit 0.
Default
0
Result
Divide by 1.
Divide by 2.
Divide by 4.
Divide by 8.
Divide by 16.
Divide by 32.
Divide by 64.
Divide by 128.
Rev. A | Page 122 of 144
Description
Serial Port Data Buffer.