ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 69

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
The ADE7566/ADE7569/ADE7166/ADE7169 achieve the
integration of the apparent power signal by continuously
accumulating the apparent power signal in an internal 48-bit
register. The apparent energy register (VAHR[23:0]) represents
the upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 34 expresses the relationship.
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7566/ADE7569/ADE7166/ADE7169 is 1.22 μs
(5/MCLK).
Figure 76 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, the internal apparent energy
register is divided by 1. VADIV is an 8-bit unsigned register.
The upper 24 bits are then written in the 24-bit apparent energy
register (VAHR[23:0]). The RVAHR register (24 bits long) is
Apparent
Apparent
Energy
Energy
=
=
∫
Apparent
lim
T
→
0
⎧
⎨
⎩
∑
n
∞
=
0
Apparent
Power
APPARENT POWER
) (
t
dt
I
Power
rms
or
T
(
nT
APPARENT
POWER SIGNAL = P
Figure 76. Apparent Energy Calculation
TIME (nT)
)
×
T
+
⎫
⎬
⎭
Rev. A | Page 69 of 144
(33)
(34)
+
48
48
23
VADIV
VAHR[23:0]
provided to read the apparent energy. This register is reset to 0
after a read operation
Note that the apparent energy register is unsigned. By setting the
VAEHF and VAEOF bits in the Interrupt Enable 2 SFR
(MIRQENM, 0xDA), the ADE7566/ADE7569/ADE7166/
ADE7169 can be configured to issue an ADE interrupt to the
8052 core when the apparent energy register is half-full or when
an overflow occurs. The half-full interrupt for the unsigned
apparent energy register is based on 24 bits as opposed to 23 bits
for the signed active energy register.
Integration Times Under Steady Load: Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 μs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the VAGAIN register set to 0x000, the
average word value from the apparent power stage is 0x1A36E2
(see the Apparent Power Calculation section). The maximum
value that can be stored in the apparent energy register before it
overflows is 2
to the internal register, which can store 2
before it overflows. Therefore, the integration time under these
conditions with VADIV = 0 is calculated as follows:
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 36.
APPARENT POWER OR I
ACCUMULATED (INTEGRATED)
IN THE APPARENT ENERGY
REGISTER
%
ADE7566/ADE7569/ADE7166/ADE7169
Time =
Time = Time
0xFFFF,
0
0xD055
24
FFFF,
or 0xFF,FFFF. The average word value is added
WDIV = 0
FFFF
0
0
rms
× VADIV
IS
×
. 1
22
μ
s
=
199
48
or 0xFFFF,FFFF,FFFF
sec
=
. 3
33
min
(35)
(36)