ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 109

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMERS
Each ADE7566/ADE7569/ADE7166/ADE7169 has three 16-bit
timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/
Counter 2. The timer/counter hardware is included on-chip to
relieve the processor core of overhead inherent in implementing
timer/counter functionality in software. Each timer/counter con-
sists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three
timers can be configured to operate as timers or as event counters.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, users can think of it as counting
machine cycles. Because a machine cycle on a single cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 102. Timer SFRs
SFR
TCON
TMOD
TL0
TL1
TH0
TH1
T2CON
RCAP2L
RCAP2H
TL2
TH2
TIMER REGISTERS
Table 103. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
Bit
7
6
5 to 4
3
2
1 to 0
Mnemonic
Gate1
C/T1
T1/M1,
T1/M0
Gate0
C/T0
T0/M1,
T0/M0
Address
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0xC8
0xCA
0xCB
0xCC
0xCD
Default
0
0
00
0
0
00
Description
Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the
TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set.
Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select Bits.
T1/M[1:0]
00
01
10
11
Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0
control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
Timer 0 Mode Select Bits.
T0/M[1:0]
00
01
10
11
Bit Addressable
Yes
No
No
No
No
No
Yes
No
No
No
No
Result
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH1 holds a value to reload into TL1 each time it overflows.
Timer/Counter 1 Stopped.
Result
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH0 holds a value to reload into TL0 each time it overflows.
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by Timer 1 control bits.
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Description
Timer/Counter 0 and Timer/Counter 1 Control (see Table 104).
Timer/Counter 0 and Timer./Counter 1 Mode (see Table 103).
Timer 0 Low Byte (see Table 107).
Timer 1 Low Byte (see Table 109).
Timer 0 High Byte (see Table 106).
Timer 1 High Byte (see Table 108).
Timer/Counter 2 Control (see Table 105).
Timer 2 Reload/Capture Low Byte (see Table 113).
Timer 2 Reload/Capture High Byte (see Table 112).
Timer 2 Low Byte (Table 111).
Timer 2 High Byte (see Table 110).
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs in Table 102.
ADE7566/ADE7569/ADE7166/ADE7169