EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 590

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–16
Arria II Device Handbook Volume 2: Transceivers
PCIe Initialization/Compliance Phase
After the device is powered up, a PCIe-compliant device goes through the compliance
phase during initialization. The rx_digitalreset signal must be de-asserted during
this compliance phase to achieve transitions on the pipephydonestatus signal, as
expected by the link layer.
The rx_digitalreset signal is de-asserted based on the assertion of the
rx_freqlocked signal.
During the initialization/compliance phase, do not use the rx_freqlocked signal to
trigger a de-assertion of the rx_digitalreset signal. Instead, perform the following
reset sequence as shown in
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. After the transmitter PLL locks, as indicated by the pll_locked signal going high
3. When the receiver CDR locks to the input reference clock, as indicated by the
PCIe Normal Phase
For the normal operation phase, perform the following reset sequence, as shown in
Figure
1. After completion of the Initialization/Compliance phase, when the rx_freqlocked
2. Wait for the rx_freqlocked signal to go high again. In this phase, the received data
3. Proceed with the reset sequence after assertion of the rx_freqlocked signal.
4. After the rx_freqlocked signal goes high, wait for at least 4 s before asserting
Data from the transceiver block is not valid from the time the rx_freqlocked signal
goes low (marker 10) to the time the rx_digitalreset is de-asserted (marker 13). The
PLD logic ignores the data during this period (between markers 10 and 13).
between markers 1 and 2). Keep the tx_digitalreset, rx_analogreset, and
rx_digitalreset signals asserted during this time period. After you de-assert the
pll_powerdown signal, the transmitter PLL starts locking to the transmitter input
reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted and for rx_analogreset to be de-asserted. After
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock.
rx_pll_locked signal going high at marker 7, de-assert the rx_digitalreset
signal (marker 8). After de-asserting rx_digitalreset, the pipephydonestatus
signal transitions from the transceiver channel to indicate the status to the link
layer. Depending on its status, pipephydonestatus helps with the continuation of
the compliance phase. After successful completion of this phase, the device enters
into the normal operation phase.
signal is de-asserted, (marker 10), wait for the rx_pll_locked signal assertion
signifying the lock-to-reference clock.
is valid (not electrical idle) and the receiver CDR locks to the incoming data.
rx_digitalreset (marker 12) for two parallel receive clock cycles so that the
receiver phase compensation FIFO is initialized.
4–10:
Figure
4–10:
Chapter 4: Reset Control and Power Down in Arria II Devices
December 2010 Altera Corporation
Transceiver Reset Sequences