EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 573

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Summary
Summary
December 2010 Altera Corporation
1
1
Even though inst0 instantiates seven transceiver channels, the ALTGX MegaWizard
Plug-In Manager provides only one bit for the pll_inclk port for inst0. In your
design, provide only one clock input for the pll_inclk port. The Quartus II software
uses two transceiver blocks to fit the seven channels and internally connects the input
reference clock (connected to the pll_inclk port in your design) to the CMU PLLs of
two transceiver blocks.
For inst1, the ALTGX MegaWizard Plug-In Manager provides a pll_inclk port. In
this example, it is assumed that a single reference clock is provided for inst0 and inst1.
Therefore, connect the pll_inclk port of inst0 and inst1 to the same input reference
clock pin to enable the Quartus II software to share a single CMU PLL in transceiver
block1 that has three channels of inst0 and one channel of inst1 (shown as ch5, ch6,
and ch7 in transceiver block 1) in
For the RX CDRs in inst0, the ALTGX MegaWizard Plug-In Manager provides seven
bits for the rx_cruclk port (if you do not select the Train Receiver CDR from
pll_inclk option in the PLL/Ports screen), allowing separate input reference clocks to
the RX CDRs of each channel.
The following summarizes how to configure multiple protocols and data rates in a
transceiver block:
■
■
■
■
■
You can run each transceiver channel at independent data rates or protocol
functional modes.
Each transceiver block consists of two CMU PLLs that provide clocks to run the
transmitter channels within the transceiver block.
To enable the Quartus II software to combine multiple instances of transceiver
channels within a transceiver block, follow the rules specified in
Requirements to Combine Channels” on page 3–2
page
You can reset each CMU PLL within a transceiver block using a pll_powerdown
signal. For each transceiver instance, the ALTGX MegaWizard Plug-In Manager
provides an option to select the pll_powerdown port. If you want to share the same
CMU PLL between multiple transceiver channels, connect the pll_powerdown
ports of the instances and drive the signal from the same logic.
If you enable the PCIe hard IP block using the PCIe Compiler, the Quartus II
software has certain requirements about using the remaining transceiver channels
within the transceiver block in other configurations. For more information, refer to
“Combining Channels Using the PCIe hard IP Block with Other Channels” on
page
3–3.
3–12.
Figure 3–6 on page
Arria II Device Handbook Volume 2: Transceivers
3–14.
and
“Sharing CMU PLLs” on
“General
3–15