EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 198

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–2
Figure 7–1. External Memory Interface Datapath Overview for Arria II GX Devices
Notes to
(1) You can bypass each register block.
(2) Shaded blocks are implemented in the I/O element (IOE).
(3) The memory blocks used for each memory interface may differ slightly.
(4) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II GX FPGA
and write operations.
Management
and Reset
Clock
Figure
7–1:
Resynchronization Clock
DQ Write Clock
DQS Write Clock
Figure 7–1
Arria II GX and Arria II GZ devices, respectively.
and
Internal Memory
Figure 7–2
(3)
Postamble Enable
Postamble Clock
show the memory interface datapath overview for
2n
Synchronization
Registers
Postamble
Control
Circuit
DLL
Chapter 7: External Memory Interfaces in Arria II Devices
2n
2
2n
DDR Input
DDR Output
DDR Output
DQS Enable
and Output
and Output
DQS Logic
Registers
Registers
Registers
Enable
Enable
Circuit
Block
(Note 1)
December 2010 Altera Corporation
,
(2)
n
n
DQS (Read) (4)
DQ (Read) (4)
DQ (Write) (4)
DQS (Write) (4)
Memory