EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 462

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Figure 1–72. SONET/SDH OC-12 Datapath
Arria II Device Handbook Volume 2: Transceivers
SONET/ SDH
1
tx_coreclk
rx_coreclk
Fabric
FPGA
SONET/SDH is one of the most common serial-interconnect protocols used in
backplanes deployed in communications and telecom applications. SONET/SDH
defines various optical carrier (OC) subprotocols for carrying signals of different
capacities through a synchronous optical hierarchy.
You can use Arria II GX and GZ transceivers as physical layer devices in a
SONET/SDH system. These transceivers provide support for SONET/SDH
protocol-specific functions and electrical features; for example, alignment to an A1A2
or A1A1A2A2 pattern.
In SONET/SDH systems, A1 is defined as 8'hF6 and A2 is defined as 8'h28. Transport
overhead bytes A1 and A2 are used for restoring frame boundary from the serial data
stream. Frame sizes are fixed, so the A1 and A2 bytes appear within the serial data
stream every 125 s. In an OC-12 system, 12 A1 bytes are followed by 12 A2 bytes.
Similarly, in an OC-48 system, 48 A1 bytes are followed by 48 A2 bytes.
OC-96 systems are for Arria II GZ devices only and have 96 A 1 bytes followed by 96
A2 bytes.
Arria II GX transceivers are designed to support the protocols OC-12 at 622 Mbps
with 8-bit channel width and OC-48 at 2488.32 Mbps with 16-bit channel width.
Arria II GZ transceivers are designed to support the protocol OC-96 at 4,967 Mbps.
Figure 1–72
mode.
FPGA Fabric-Transmitter
FPGA Fabric-Receiver
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-12
rx_clkout
Compensation
tx_clkout
RX Phase
FIFO
Compensation
wrclk
TX Phase
FIFO
rdclk
Transmitter Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
Parallel Recovered Clock
Aligner
Word
Chapter 1: Transceiver Architecture in Arria II Devices
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Serializer
Divider
Local
Clock
December 2010 Altera Corporation
CDR
High-Speed
Serial Clock
Functional Modes