EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 515

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–16. Receiver Datapath Clocking in ×4 Bonded Channel Configurations Without Deskew FIFO
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
x4 Bonded Channel Configurations Without Deskew FIFO
PCIe ×4 functional modes have ×4 bonded channel configurations without deskew
FIFO.
Figure 2–16
without deskew FIFO.
PCIe
PCIe
PCIe
PCIe
coreclkout
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
shows receiver datapath clocking in ×4 channel bonding configurations
Channel 3
Channel 2
Channel 1
Channel 0
Input Reference Clock
Input Reference Clock
/2
/2
/2
/2 /2
/2
CMU1_PLL
CMU0_PLL
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
CMU1 Clock Divider
CMU0 Clock Divider
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric-Transceiver Interface Clock
Parallel Recovered Clock
Low-Speed Parallel Clock from CMU0 Clock Divider
Serial Recovered Clock
Ch2
Ch1
Ch0
3h0
CMU1_Channel
CMU0_Channel
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
Clock
Clock
Clock
Clock
Input
Input
Input
Input
2–25