EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 190

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–32
Figure 6–15. LVDS I/O Standard Termination for Arria II Devices
Note to
(1) For LVDS output with a three-resistor network, the R
(2) LVDS_E_1R is available for Arria II GZ devices only.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
the R
Figure
P
value is 120 Ω.
LVDS_E_3R) (1)
with One-Resistor
External On-Board
(Single-Ended
OCT Receive
6–15:
LVDS Output
(Single-Ended
OCT Receive
LVDS_E_1R)
with Three
LVDS Output
OCT Receive
Network,
Termination
Resistor
(True LVDS
Termination
Network,
Output)
(1), (2)
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O (GPIO) interface standard. Arria II LVDS I/O standard requires
a 2.5-V V
100-Ω termination resistor between the two signals at the input buffer. Arria II devices
provide an optional 100-Ω differential termination resistor in the device with
R
Figure 6–15
R
D
D
OCT.
OCT is only available in the row I/O banks.
CCIO
Single-Ended Outputs
Single-Ended Outputs
Differential Outputs
Differential Outputs
shows the details of LVDS termination in Arria II devices. The Arria II GZ
level. The LVDS input buffer requires 2.5-V V
S
and R
P
values are 120 and 170 Ω , respectively. For LVDS output with a one-resistor network,
External Resistor
≤ 1 inch
External Resistor
Rs
Rs
Rp
Rp
(Note 1)
50 Ω
LVDS
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
Chapter 6: I/O Features in Arria II Devices
100 Ω
100 Ω
100 Ω
Termination Schemes for I/O Standards
CCPD
December 2010 Altera Corporation
Differential Inputs
Differential Inputs
Differential Inputs
Differential Inputs
. LVDS requires a
Arria II OCT
Arria II OCT
Arria II OCT