EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 492
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EP2AGX95EF29C4N
Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29C4N.pdf
(306 pages)
Specifications of EP2AGX95EF29C4N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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2–2
Figure 2–1. Input Reference Clock Sources in a Transceiver Block
Note to
(1) One global clock line is available for each CMU PLL and receiver CDR in a transceiver block. This configuration allows each CMU PLL and receiver
Arria II Device Handbook Volume 2: Transceivers
CDR to derive its input reference clock from a separate FPGA CLK input pin.
refclk0
refclk1
Figure
2–1:
/2
/2
Figure 2–1
within a transceiver block.
shows the input reference clock sources for CMU PLLs and receiver CDRs
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
Global Clock Line (1)
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
CMU PLL and Receiver CDR Input Reference Clocking
Chapter 2: Transceiver Clocking in Arria II Devices
CMU1 PLL
CMU0 PLL
CDR
CDR
CDR
CDR
December 2010 Altera Corporation
Transceiver Block
CMU1 Block
CMU0 Block
Channel 3
Channel 2
Channel 1
Channel 0
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