EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 246

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–6
Table 8–2. LVDS Channels Supported in Arria II GX Device Column I/O Banks
2)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Notes to
(1) There are no dedicated SERDES and DPA circuitry in device column I/O banks.
(2) R
(3) Rx = True LVDS input buffers without R
(4) Tx = True LVDS output buffers.
(5) eTx = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
EP2AGX260
Device
D
= True LVDS input buffers with R
Table
8–2:
358-Pin FlipChip UBGA
Table 8–3
supported in Arria II GZ devices.
Table 8–3. LVDS Channels Supported in Arria II GZ Device Row I/O Banks
Table 8–4. LVDS Channels Supported in Arria II GZ Device Column I/O Banks
Notes to
(1) Rx = true LVDS input buffers with R
(2) The LVDS receiver (Rx) and Tx channels are equally divided between the left and right sides of the device, except for
(3) The LVDS channel count does not include dedicated clock input pins.
Notes to
(1) Rx = true LVDS input buffers without R
(2) The LVDS Rx and Tx channels are equally divided between the top and bottom sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
EP2AGZ225
EP2AGZ300
EP2AGZ350
EP2AGZ225
EP2AGZ300
EP2AGZ350
Device
Device
—
LVDS_E_1R or LVDS_E_3R).
the devices in the 780-pin Fineline BGA. These devices have the LVDS Rx and Tx located on the left side of the device.
LVDS_E_3R).
Table
Table
D
and
OCT support.
D
8–3:
8–4:
OCT support.
Table 8–4
68(Rx or eTx) + 72 eTx
68(Rx or eTx) + 72 eTx
780-Pin FineLine BGA
780-Pin FineLine BGA
572-Pin FlipChip FBGA
—
—
—
—
list the maximum number of row and column LVDS I/Os
—
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
D
OCT, Tx = true LVDS output buffers, eTx = emulated LVDS output buffers (either
D
OCT, eTx = emulated LVDS output buffers (either LVDS_E_1R or
1152-Pin FineLine BGA
1152-Pin FineLine BGA
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
42(Rx or eTx) +
42(Rx or eTx) +
42(Rx or eTx) +
780-Pin FlipChip FBGA
44(Tx or eTx)
44(Tx or eTx)
44(Tx or eTx)
56(Rx, Tx, or eTx)
57(R
(Note
D
or eTx) +
1), (2), (3), (4), (5),
December 2010 Altera Corporation
1517-Pin FineLine BGA
1517-Pin FineLine BGA
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
93(Rx or eTx) + 96 eTx
(Note
Locations of the I/O Banks
(Note
1152-Pin FlipChip FBGA
86(Rx or eTx) +
86(Rx or eTx) +
86(Rx or eTx) +
88(Tx or eTx)
88(Tx or eTx)
88(Tx or eTx)
1), (2),
96(Rx, Tx, or eTx)
97(R
1), (2),
(6)
(Part 2 of
D
or eTx) +
(3)
(3)