EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 540

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–50
Figure 2–28. Sixteen Non-Bonded Receiver Channels without Rate Matcher for Example 8
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Consider 16 non-bonded receiver channels without a rate matcher located across
four transceiver blocks, as shown in
16 channels has a 0 PPM frequency difference with respect to each other. The
Quartus II software uses rx_clkout from each channel to clock the read port of its
receiver phase compensation FIFO, resulting in 16 clocks resources (global,
regional, or both) being used, one for each channel.
Example 8: Sixteen Channels Across Four Transceiver Blocks
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
rx_clkout[15]
rx_clkout[14]
rx_clkout[13]
rx_clkout[12]
rx_clkout[11]
rx_clkout[10]
rx_clkout[9]
rx_clkout[8]
rx_clkout[7]
rx_clkout[6]
rx_clkout[5]
rx_clkout[4]
rx_clkout[3]
rx_clkout[2]
rx_clkout[1]
rx_clkout[0]
rx_coreclk[15]
rx_coreclk[11]
rx_coreclk[7]
rx_coreclk[3]
rx_coreclk[14]
rx_coreclk[13]
rx_coreclk[12]
rx_coreclk[10]
rx_coreclk[9]
rx_coreclk[8]
rx_coreclk[6]
rx_coreclk[5]
rx_coreclk[4]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
Figure
2–28. The incoming serial data for all
Chapter 2: Transceiver Clocking in Arria II Devices
Channel [15:12]
Channel [11:8]
Channel [7:4]
Channel [3:0]
and Status
and Status
and Status
and Status
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
FPGA Fabric-Transceiver Interface Clocking
FPGA Fabric
December 2010 Altera Corporation