EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 519

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–9. FPGA Fabric-Transceiver Interface Clocks for Arria II Devices (Part 1 of 2)
December 2010 Altera Corporation
Clock Name
pll_inclk
rx_cruclk
tx_clkout
Phase Compensation FIFO Clocks
Other Transceiver Clocks
Receiver CDR input reference clock when
The input reference clock follows these guidelines:
■
■
■
The transmitter and receiver phase compensation FIFOs in each channel ensure the
reliable transfer of data, control, and status signals between the FPGA fabric and the
transceiver channels. The transceiver channel forwards the tx_clkout signal (in
non-bonded modes) or the coreclkout signal (in bonded channel modes) to the FPGA
fabric to clock the data and control signals into the transmitter phase compensation
FIFO. The transceiver channel also forwards the recovered clock rx_clkout (in
configurations without rate matcher) or tx_clkout/coreclkout (in configurations
with rate matcher) to the FPGA fabric to clock the data and status signals from the
receiver phase compensation FIFO into the FPGA fabric.
The phase compensation FIFO clocks form a part of the FPGA fabric-transceiver
interface clocks and are routed on either a global clock resource, regional clock
resource, or periphery clock resource in the FPGA fabric.
The following transceiver clocks form a part of the FPGA fabric-transceiver interface
clocks:
■
■
The Quartus II software automatically routes fixed_clk on the FPGA fabric global
clock or regional clock network.
Table 2–9
CMU PLL input reference clock when
driven from an FPGA CLK input pin
driven from an FPGA CLK input pin
Phase compensation FIFO clock
If the input reference clock to the CMU PLL or receiver CDR is provided through
the FPGA CLK input pins or the clock output from the left PLLs in the FPGA fabric,
the input reference clock becomes a part of the FPGA fabric-transceiver interface
clocks.
If the input reference clock is provided through the FPGA CLK input pins, the
Quartus II software automatically routes the input reference clock on the FPGA
fabric global clock network.
If the input reference clock is provided through the output clock from a left PLL,
the Quartus II software routes the input reference clock on a dedicated clock path
from the left PLL to the CMU PLL or receiver CDR.
cal_blk_clk—calibration block clock
fixed_clk—125 MHz fixed-rate clock used in PCIe receiver detect circuitry
Clock Description
lists the FPGA fabric-transceiver interface clocks.
Transceiver-to-FPGA fabric
FPGA fabric-to-transceiver
FPGA fabric-to-transceiver
Interface Direction
Arria II Device Handbook Volume 2: Transceivers
Resource Utilization
FPGA Fabric Clock
Global, Regional,
Periphery clocks
Global clock
Global clock
(1)
2–29