PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 86
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PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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PN512
Product data sheet
COMPANY PUBLIC
12.6.1 Signal shape for Felica S
The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal is combined by using the
logical function exclusive or.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for that digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register TxSelReg controls the setting at SIGOUT.
The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver.
The modulation is done according to the register settings of the antenna drivers.
The clock is switched to AUX1 or AUX2 (see AnalogSelAux).
Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at
SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock
output if a serial interface is used. The HIGH level at D0 is the same as PVDD.
Note: The signal on the antenna is shown in principle only. In reality the waveform is
sinusoidal.
Fig 30. Signal shape for SIGOUT in FeliCa card SAM mode
Fig 31. Signal shape for SIGIN in SAM mode
demodulated
signal on
signal on
antenna
signal on
SIGOUT
SIGIN
clock
signal
clock
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
2
C interface support
111336
Transmission module
© NXP B.V. 2011. All rights reserved.
PN512
001aan227
001aan228
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