PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 58

• Manufacturer Part Number: PN5120A0HN/C1
• Description: Transmission Module 40-Pin HVQFN EP T/R
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1

• Package: 40HVQFN EP
• Operating Temperature: -30 to 85 °C

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.4.2 TestSel1Reg
9.2.4.3 TestSel2Reg
General test signal configuration.
Table 112. TestSel1Reg register (address 31h); reset value: 00h, 00000000b
Table 113. Description of TestSel1Reg bits
General test signal configuration and PRBS control
Table 114. TestSel2Reg register (address 32h); reset value: 00h, 00000000b
Table 115. Description of TestSel2Reg bits
Bit
7 to 6
5 to 4
3
2 to 0
Bit
7
6
5
4 to 0
Access
Rights
Access
Rights
TstBusFlip
Symbol
-
SAMClockSel
SAMClkD1
TstBusBitSel
Symbol
TstBusFlip
PRBS9
PRBS15
TestBusSel
r/w
7
-
r/w
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
r/w
PRBS9
6
-
r/w
Description
Reserved for future use.
Value
00
01
10
11
Set to logic 1, the SAM clock is delivered to D1.
Note: Only possible if the 8bit parallel interface is not used.
Select the TestBus bit from the testbus to be propagated to SIGOUT.
Description
If set to logic 1, the testbus is mapped to the parallel port by the
following order:
D4, D3, D2, D6, D5, D0, D1. See
Starts and enables the PRBS9 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS9 mode.
Note: The data transmission of the defined sequence is started by the
send command.
Starts and enables the PRBS15 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS15 mode.
Note: The data transmission of the defined sequence is started by the
send command.
Selects the testbus. See
Defines the source for the 13.56 MHz SAM clock
6
111336
PRBS15
r/w
SAMClockSel
5
r/w
Description
GND- Sam Clock switched off
clock derived by the internal oscillator
internal UART clock
clock derived by the RF field
5
r/w
4
r/w
4
Section 20 “Testsignals”
SAMClkD1
r/w
r/w
3
3
Section 20
TestBusSel
r/w
r/w
2
2
“Testsignals”.
Transmission module
TstBusBitSel
© NXP B.V. 2011. All rights reserved.
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