PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 111
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PN5120A0HN/C1
Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN/C1
Package
40HVQFN EP
Operating Temperature
-30 to 85 °C
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Product data sheet
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25.2.2.2 Bus timing for common Read/Write strobe
Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care.
For the multiplexed address and data bus the address lines A0 to A3 have to be
connected as described in chapter Automatic host controller Interface Type Detection.
Table 173. Timing specification for common Read/Write strobe
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX
LLSL
CLSL
SHCH
SLDV,R
SHDZ
DVSH
SHDX
SHRX
SLSH
AVSL
SHAX
Fig 40. Timing diagram for separated Read/Write strobe
D0...D7
A0...A3
NWR
NRD
NCS
ALE
Parameter
AS pulse width
Multiplexed Address Bus valid to AS low (Address Set Up Time) 5
Multiplexed Address Bus valid after AS low (Address Hold Time) 5
AS low to NDS low
NCS low to NDS low
NDS high to NCS high
NDS low to DATA valid (for read cycle)
NDS low to DATA high impedance (read cycle)
DATA valid to NDS high (for write cycle)
DATA hold after NDS high (write cycle, Hold Time)
R/NW hold after NDS high
NDS pulse width
Separated Address Bus valid to NDS low (Hold Time)
Separated Address Bus valid after NDS high (Set Up Time)
All information provided in this document is subject to legal disclaimers.
multiplexed
addressbus
A0...A3
Rev. 3.6 — 10 March 2011
t
LHLL
t
AVLL
111336
t
LLAX
t
WHWL
SEPARATED ADDRESSBUS A0...A3
t
LLWL
t
AVWL
t
CLWL
t
t
WLDV
RLDV
t
WLWH
D0...D7
Transmission module
Min
10
10
0
0
-
-
5
5
5
40
30
5
© NXP B.V. 2011. All rights reserved.
t
WHCH
t
WHAX
PN512
t
t
t
WHDX
RHDZ
Max
-
-
-
-
-
-
35
10
-
-
-
-
-
-
WHWL
001aan233
111 of 125
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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