PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 29

• Manufacturer Part Number: PN5120A0HN/C1
• Description: Transmission Module 40-Pin HVQFN EP T/R
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1

• Package: 40HVQFN EP
• Operating Temperature: -30 to 85 °C

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.1.12 WaterLevelReg
9.2.1.13 ControlReg
Defines the level for FIFO under- and overflow warning.
Table 38.
Table 39.
Miscellaneous control bits.
Table 40.
Table 41.
Bit
7 to 6
5 to 0
Bit
7
6
5
4
3
2 to 0
Access
Rights
Access
Rights
Symbol
TStopNow
TStartNow
WrNFCIDtoFIFO
Initiator
-
RxLastBits
TStopNow TStartNow
Symbol
-
WaterLevel
WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
Description of WaterLevelReg bits
ControlReg register (address 0Ch); reset value: 00h, 00000000b
Description of ControlReg bits
RFU
7
0
w
7
All information provided in this document is subject to legal disclaimers.
RFU
Rev. 3.6 — 10 March 2011
6
0
Description
Reserved for future use.
This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see
w
6
Description
Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
Reserved for future use.
Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.
111336
r/w
WrNFCIDtoFIFO
5
dy
5
r/w
4
Initiator
r/w
r/w
3
WaterLevel
4
RFU
3
0
r/w
2
Transmission module
2
r
© NXP B.V. 2011. All rights reserved.
Table 30
r/w
RxLastBits
1
PN512
1
r
29 of 125
r/w
0
0
r